Highest Voted 'spartan' Questions

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Implement high impedance 'Z' input output property with chisel

My board (apf27) has a processor (i.MX27) and a FPGA (Spartan3A) that communicate through a "memory bus" called WEIM in proc datasheet. I want to transfer data from the FPGA to the processor. I managed to do it with a simple Output() IO : val io =…

fpga chisel spartan

asked May 15 '18 at 12:06

FabienM

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Adding Integers Problems in VHDL Spartan 3

I have a problem trying to add my integer signal and trying to decode it on my segment. BTW, our project is try to display the incremented value when one switch is click. There are 3 switches (swA,swB,swC). Initially, all 3 segments are 0,0,0 if you…

vhdl fpga spartan

asked Jul 18 '17 at 05:56

Johnny

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Displaying different numbers on 2 seven segment displays on VHDL (Spartan 3)

We have an assignment about decoding. 4 input switches (binary combination) and displays the corresponding switch combination to 4-LED and decimal value to 1 seven-segment. And convert those binary combination to Grey Code (4 bit also) and display…

vhdl xilinx-ise spartan

asked Jul 12 '17 at 17:19

Johnny

45
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xil_cache error in Xilinx SDK

I am working on a small project of mine on Digilent Atlys and after all of the standard generating the netlist and bitstream, and exporting to SDK, I happen to get a weird error which states that the xil_cache.h is not present anywhere (even though…

fpga xilinx xilinx-ise spartan xilinx-edk

asked Mar 02 '17 at 09:08

Joe Carr

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VHDL code not working on board but works on simulation

i'm working on a project using vhdl to configure a fpga board spartan 3E. what i have to do is a genius puzzle, in my main code there is a state machine to control the logic. everything works well when i simulate the code using xilinx simulator but…

vhdl fpga xilinx xilinx-ise spartan

asked Nov 27 '16 at 16:12

Andrey Viktor Kandauroff

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How to find the VCC routing in FPGA bitstream

i have a spartan3e FPGA, i built a 2 bit counter with it, and generated the corresponding xdl file with "xdl -ncd2xdl". in the xdl file, i found the following program: inst "XDL_DUMMY_CLB_X1Y22_VCC_X2Y24" "VCC",placed CLB_X1Y22 VCC_X2Y24 , cfg…

fpga spartan

asked Jul 30 '16 at 22:56

typen

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Xilinx Floating Point Core - Erroneous 'X' values?

I've attempted to use the Xilinx pg060 Floating Point Core. After looking through the diagrams provided, such as the timing diagram above and the demo testbench (which for the inexperienced such as myself, is quite confusing!) I created a short…

floating-point vhdl multiplication xilinx-ise spartan

asked Apr 14 '16 at 17:30

davidhood2

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Serializing code in VHDL

I'm attempting to create a (very basic) GPU on a Spartan-6 FPGA using VHDL. The big problem I have hit upon is that my understanding of HDL is quite limited - I've been writing my code using nested for loops for ray tracing/scanline rasterization…

for-loop vhdl fpga rasterizing spartan

asked Apr 05 '16 at 09:13

davidhood2

1,367
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Suboptimal Timing Implementation Warning - F7 Multiplexer

I'm attempting to create an I2C bus for testing as part of my attempt to program a DVI Ch7301c. I'm supplying it with test data, however, when I try and transmit the data values hex 77, it throws this warning: Pack:2574 - The F7 multiplexer symbol …

vhdl timing xilinx synthesis spartan

asked Nov 30 '15 at 22:31

davidhood2

1,367
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Changing Counter target according to input

I'm working on a project for a digital design course, and I have to play musical notes using frequencies in my project. I must say I'm fairly inexperienced in verilog (have to use verilog for the project). I researched a bit regarding the topic and…

verilog fpga spartan

asked Nov 24 '15 at 08:29

A. Wali

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Does the PERIOD keyword in the UCF file specify or inform

My board (Papilio One 500k) has a 32 MHz on-board oscillator that is connected to P89. I see in the default constraints (UCF) file I downloaded, it has the line: NET CLK LOC="P89" | IOSTANDARD=LVTTL | PERIOD = 31.25 ns; Now, why is it that the…

vhdl fpga xilinx spartan

asked Nov 21 '15 at 01:06

Terry Price

337
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Code to test ps/2 on verilog

I have a logitech keyboard with a ps/2 connection. I also have a Baysis2 fpga that I would like to use to read keyboard input. The problem is, the keyboard doesn't seem to be receiving power. I may be wrong, but non of the lights on the keyboard…

keyboard verilog fpga spartan ps2

asked Nov 20 '15 at 22:04

Noah Mendoza

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Accessing Spartan-6 ODDR & other selectIO library designs in ISE

I'm writing a program to hopefully eventually communicate with the DVI codec on the SP605 board. However, I am having problems outputting a differential clock to the DVI codec that is required and, it appears I need to use a ODDR2 in order to do…

vhdl clock xilinx spartan

asked Nov 18 '15 at 15:17

davidhood2

1,367
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Setting FPGA clock frequency using Timing Constraints

I am (slowly) moving my way through an "introductory" course on FPGA programming using Xilinx Spartan-6 Eval Board, and am looking at clock timings and how you can add necessary timing constraints. It has led me to a couple of questions. For this…

constraints vhdl clock xilinx spartan

asked Nov 02 '15 at 20:39

davidhood2

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Import Code from FPGA Board (Spartan 3E)

Is there any way to import code from an already programmed FPGA board, in this case, it is a Spartan 3E board. That is to say, verilog code has already been uploaded to it, so I would like a way to receive the code back in the computer since I have…

hardware verilog vhdl fpga spartan

asked Jul 27 '10 at 07:49

intl

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Questions tagged [spartan]