Setting FPGA clock frequency using Timing Constraints

Question

I am (slowly) moving my way through an "introductory" course on FPGA programming using Xilinx Spartan-6 Eval Board, and am looking at clock timings and how you can add necessary timing constraints. It has led me to a couple of questions. For this demonstration I have used a simple program to just make an LED blink (code at the bottom).

I then added this constraint to my constraints file:

NET "CLK" TNM_NET = CLK;
TIMESPEC TS_CLK = PERIOD "CLK" 200 MHz HIGH 50%; # What effect does the 200 Mhz enforce?

What does the constraint actually enforce? Because when I attempt to scale it in order to make an LED blink at 1 Hz I find it makes no difference whether I put a timing constraint of 200 MHz, or any other number!

Thanks very much! My entire source code is below for reference.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LED_Blink is
    port(
        CLK : in  std_logic;
        LED        : out std_logic
    );

end LED_Blink;

architecture Behavioral of LED_Blink is
    signal CLK_1Hz : std_logic;
    signal counter : std_logic_vector(26 downto 0);
begin
    prescaler : process(CLK)
    begin
        if rising_edge(CLK) then
            if (counter < 1000000) then --possibly change to number in binary
                counter <= counter + 1;
            else
                CLK_1Hz <= not CLK_1Hz;
                counter <= (others => '0');
            end if;
        end if;
    end process;

    LED <= CLK_1Hz;

end Behavioral;

NET "CLK" LOC ="K21";
NET "LED" LOC = "D21";
NET "CLK" TNM_NET = CLK;
TIMESPEC TS_CLK = PERIOD "CLK" 5 ns HIGH 50%;

Not sure why this deserves downvote - could at least comment so I can improve the question as per the help centre guide! — davidhood2, Nov 02 '15 at 21:38
I didn't downvote but you should probably split it into two separate questions, and I'm not sure your second question is really on topic. Also you probably shouldn't just use the raw input clock, you can instantiate a PLL in the device. — Bob, Nov 02 '15 at 21:41

score 3 · Accepted Answer · answered Nov 02 '15 at 21:53

Timing constraint are parameters for Static Timing Analysis (STA). An STA tool like Xilinx trace can tell you if your code - generated, mapped, placed and finally routed netlist - will meet all timing requirements.

Every part of your described circuit (LUTs, registers and wires) has a delay. STA ensures you that the overall delay is less than your clock period minus some uncertenty. (see the Xilinx timing guide for more information on 'setup' and 'hold' times.)

So setting CLK to 200 MHz checks if your circuit will run at up to 200 MHz. It does not change the behavior like a blinking frequency.

Setting FPGA clock frequency using Timing Constraints

1 Answers1