Highest Voted 'spartan' Questions

0

votes

1 answer

I want to order two signals to one input in vhdl

I want to have two signals (overflow1 and set1) for one input(tick). counter2 : counter generic map (border => 5, width => 4) port map (RST => RST, tick => overflow1 [...] set1, -- overflow1 and set1 are these signals enable => SW0, …

vhdl xilinx spartan

asked Aug 01 '13 at 08:53

Alex Heintz

33
4

0

votes

2 answers

Trying to implement spi bus in vhdl

I've been trying to comunicate with the LTC2426 DAC via SPI and I've failed missrebly. Now I'm seeking for help. Could someone tell me why my code doesn't work. The CSDAC Works properly the SCLK is generated and the 32 bits are sent but still I may…

vhdl fpga spi dac spartan

asked Jul 04 '13 at 18:50

gv260ea

21
1
5

0

votes

2 answers

Bug in UCF file creation?

Creating Microbalze using EDK creates a ucf file in the data folder in the same directory , after creating a simple microblaze on spartan 6 using ethernet , and ddr3 IPS i opened UCF file: # Spartan-6 SP605 Evaluation Platform Net…

vhdl pins spartan

asked Jun 10 '13 at 12:59

Omar shaaban

257
3
19

0

votes

2 answers

Send UDP packet to fpga spartan 3e via ethernet

I want to send UDP packet to fpga which includes microblaze. But i have a problem about ip address. Where can i get the ip address of fpga.

udp ethernet fpga microblaze spartan

asked Apr 02 '13 at 09:52

kgnkbyl

737
1
5
16

0

votes

3 answers

high frequency from low frequency clock

My spartan 3a fpga board has a 50mhz clock while implementing a microblaze with ram ddr2 , it required a frequency of 62mhz which was edited by my program , when asked about this , they told me that 60mhz clock is used to generate other clocks…

vhdl clock fpga spartan

asked Apr 01 '13 at 03:56

Omar shaaban

257
3
19

0

votes

2 answers

Counter with push button switch design using VHDL and Xilinx

I'm very new to VHDL and XILINX ISE. I use the version 13.2 for Xilinx ISE. I want to design a very simple counter with the following inputs: Direction Count The count input will be assigned to a button and I want the counter to count up or down…

vhdl fpga xilinx spartan

asked Mar 18 '13 at 18:10

Varaquilex

3,447
7
40
60

0

votes

1 answer

chdir not working on Spartan 6 SP605 FPGA

I am working on a project that uses the Spartan 6 FPGA eval kit. The problem I am having is that when trying to change the directory on the CF card, the software can't build the working stack. The directory is "a:\\setup" and that is being passed to…

fpga xilinx chdir spartan

asked Dec 14 '12 at 17:35

RXC

1,233
5
36
67

0

votes

1 answer

How to read and write using block ram?

How to read and write using block ram in spartan 3? I read in sim.pdf a manual of xilinix that each write needs one clock cycle and each read too as the BRAMs are synchronus. Are we supposed to make a finite state machine free each of the write and…

vhdl fpga xilinx hdl spartan

asked Jul 03 '12 at 23:47

BlueHorse

1
1
1

0

votes

1 answer

Verilog: Pass a vector as a port to a module

I have two modules counter: Output is a vector called error_count. lcd: Module to display the code on an LCD. Input includes clock and error_count. Following snippet of the code is most relevant and attached below: Top level module: counter…

module verilog xilinx lcd spartan

asked May 20 '12 at 09:32

Neel Mehta

278
6
17

-1

votes

1 answer

Program Spartan6 eFUSE key in w10

I need help programing efuse registers on Spartan 6 from windows 10. We have plethora of boards designed with the Spartan 6. We are currently programming them with an old Windows XP machine which needs to be retired and replaced with windows…

xilinx-ise jtag spartan

asked Jul 26 '21 at 12:34

Joshua

1,185
14
23

-1

votes

1 answer

verilog code is working in isim(xilinx 14.2) but is not working onspartan6

i have written a simple counter code in verilog (xilix 14.2). The code is working properly in the isim but i am not able to dump it onto spartan6. When I try to do dump the code, a red light is ON , on the spartan 6 and the code is not dumped .…

verilog fpga xilinx-ise spartan

asked Dec 07 '18 at 16:57

user10759984

-1

votes

2 answers

How to run an Arduino project on an FPGA

I have an Arduino project and I want to run it on an FPGA (I prefer a Spartan Board), but i am not familiar with a method doing something like that. Can anyone help me?

arduino fpga xilinx spartan

asked Nov 27 '13 at 10:22

an an

49
2
7

-2

votes

1 answer

Selecting a package in Xilinx ISE project: FPGA Spartan 3 Device XC3S200

While creating project in Xilinx ISE, we have to select a package in project setting after choosing Family and device. Could any one help me, how I can select/know the package in Xilinx ISE project setting for FPGA Spartan 3 Device XC3S200. Thanks…

fpga xilinx spartan

asked Jan 22 '18 at 19:18

Chand Baba

31
1
6

-3

votes

1 answer

I m trying to synthetize any simple project in ISE for virtex 6. When I generated my synthesis report ,no minimum period was calculated

I am running a project on xilinx 14,1 in virtex 6 . I generated synthesis report. while viewing i couldn't find minimum period.. please help? Speed Grade: -3 Minimum period: No path found Minimum input arrival time before clock: 15.397ns Maximum…

verilog fpga xilinx spartan virtex

asked Apr 10 '18 at 20:16

Vaibhav Gera

1
2

-3

votes

1 answer

how to write code for this?

In Verilog HDL describe a hardware that is able to generate a clock frequency f 0 of approximately 3Hz. Display this clock by connecting it to LED LD7 to verify your approach. I tried a lot but not able to get right output. Device:-Basys2 Spartan3e

verilog fpga xilinx spartan

asked Nov 12 '15 at 19:33

Massnk Dev

19
1
6

Questions tagged [spartan]