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i have a spartan3e FPGA, i built a 2 bit counter with it, and generated the corresponding xdl file with "xdl -ncd2xdl". in the xdl file, i found the following program:

inst "XDL_DUMMY_CLB_X1Y22_VCC_X2Y24" "VCC",placed CLB_X1Y22 VCC_X2Y24 , cfg "_NO_USER_LOGIC:: _VCC_SOURCE::VCCOUT " ; net "GLOBAL_LOGIC1_0" vcc, outpin "XDL_DUMMY_CLB_X1Y22_VCC_X2Y24" VCCOUT , inpin "out_0" BY , pip CLB_X1Y22 BY3 -> BY_PINWIRE3 , pip CLB_X1Y22 VCC_PINWIRE -> BY3 , ;

however when i turn these two statements off, i can't find any change in the bitstream file. is there any bits in the spartan3e bitstream that map to the above statments? i'm really puzzled because i suppose there should be some bits in relation with this VCC routing, but in fact i can't find any...

thanks.

typen
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  • What does this VCC route connect to in the design? A LUT4 input? Something in the carry chain? In some cases the software may want to have a "dummy" VCC connection/primitive when in reality the VCC is just generated at some configuration cell in the CLB you're interested in. – nanofarad Aug 11 '16 at 17:32
  • @hexafraction, the VCC is connected to the "D" of a FF in the SLICE. and it looks like the VCC is always there no matter you connected it or not. may be it is the way you call it a "dummy VCC". – typen Sep 07 '16 at 20:11

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