1

My board (Papilio One 500k) has a 32 MHz on-board oscillator that is connected to P89.

I see in the default constraints (UCF) file I downloaded, it has the line:

NET CLK   LOC="P89" | IOSTANDARD=LVTTL | PERIOD = 31.25 ns;

Now, why is it that the period is defined here as 31.25 ns.

If the on board oscillator is a set frequency, why is it I can set the period here?

My thought is that this statement is to inform the compiler of the period of the on board oscillator rather than specify what the period is.

Paebbels
  • 15,573
  • 13
  • 70
  • 139
Terry Price
  • 337
  • 2
  • 8

1 Answers1

1

You can also set the frequency in an UCF file. Here is an example:

NET "SystemClock_200MHz_p"  LOC = "H9";         ## U64.4
NET "SystemClock_200MHz_n"  LOC = "G9";         ## U64.5
NET "SystemClock_200MHz_?"  IOSTANDARD = LVDS;
NET "SystemClock_200MHz_p"  TNM_NET = "NET_SystemClock_200MHz";

TIMESPEC "TS_SystemClock"   = PERIOD "NET_SystemClock_200MHz" 200 MHz HIGH 50 %;

The period in your code is set to 31.25 ns, because that's the period of a 32 MHz clock signal.

Period := 1/Frequency

Yes, the constraint has no physical impact to the board or oscillator. It's needed by the static timing analyzer (STA) to check if your design meets all timing requirements (e.g. setup and hold times).

Paebbels
  • 15,573
  • 13
  • 70
  • 139
  • Well, what happens if I set it to value that's not the frequency of the on board oscillator? What if it's higher? lower? – Terry Price Nov 21 '15 at 01:46
  • 1
    If it's higher and the tools meet that spec, great! You can increase the clock rate if you want. If it's lower than your actual clock, there are no guarantees your design will work. Do you feel lucky? –  Nov 21 '15 at 10:37
  • The setting also drives the place and route to insure that all the logic and routing delays are short enough to "meet timing". All combinatorial logic must settle and the outputs arrive at all the destination registers before the next clock arrives. So if there is plenty of timing "slack", the logic and flip flops can be scattered around the FPGA wherever. If you try to compile the design for a really high clock rate (short period), it may take too long to route or fail timing. If it is lower than the real clock, some signals may be unstable when they are latched and give random behavior. – Anders Dec 10 '15 at 04:33