Issue with CSRR instruction in RISCV

Question

I am working on verifying access modes for RISCV CSRs while i am verifying Machine mode Read ony CSRs in assembly code, when i try to access Machine Mode CSR it needs to raise exception but in my case i placed two back to back CSRR insruction where it raised exception for first CSR for other it didn't raise exception. I tried it by placing CSRR in last insrtuction there also it didn't raised exception.

please find the code i am using for your reference.

la x6, supervisor_exception_handler  
    csrw mtvec, x6     ## Writing address of the exception handler into MTVEC
csrr x30, 0x341    ## Reading initial value MEPC CSR
csrr x31, 0x342    ## Reading initial value of MCAUSE CSR

# Save the MSTATUS current mode in x28
    csrr x28, 0x300
    # Set the MPP field to supervisor mode (1)
    li x29, 0b1
    slli x29, x29, 11
    addi x28, x29, 0

    # Write the modified MSTATUS value back to the CSR
    csrw 0x300, x28
    # Writing supervisor starting value to MEPC 
la x28, supervisor_code
    csrw 0x341, x28

csrr x31, 0x300

mret

   # Supervisor code starts here

supervisor_code: csrr x6, 3860 li x7, 0x00000000 bne x6, x7, csr_fail

csrr x6, 3860
li x7, 0x00000000
bne x6, x7, csr_fail

li x5, 0xa5a5a5a5
csrrw x1, 3860, x5
li x5, 0x00000000
bne x5, x1, csr_fail

li x5, 0x5a5a5a5a
csrrw x1, 3860, x5
li x5, 0x00000000
bne x5, x1, csr_fail

supervisor_exception_handler: csrr x30, 0x341 ## Reading MEPC CSR which holds exception origin Address
csrr x31, 0x342 ## Reading MCAUSE CSR which holds the cause of exception li x2 ,2 beq x31, x2, next_iter1 ## Checking is exception is expected exception or not j csr_fail

next_iter1: csrw 0x342, 0 ## Reseting MCAUSE value to 0 before handling new exception beq x30, x0, csr_fail addi x7, x30, 12 jr x7 ## Jump to MEPC + 12 Address location

As shown in above it is raising exception for first CSRR instruction but for second CSRR it is not raising exception. for csrrw instructions it is raising exception, could anyone please help me in understanding this issue.

Thanks

Issue with CSRR instruction in RISCV

0 Answers0