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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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Data transfer between host and endpoint using PCIe

Last few days onwards I am trying to develop data transfer between the host and endpoint, but I am unable to do that implementation.I have tried how to read the configure space using some calls(pci_read_long),it is successfully reading the data like…
sravan
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How to detect Intel Xeon Phi coprocessor on Windows?

Is there any C/C++ API's which I can use to detect whether the system has a xeon phi co-processor in it?
nithinj
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make a program see a PCIe card that has been programmed to detect PCI

I have a 3rd party propriety software that was on some old hardware, this box also had a PCI SCSI card that plugged into a special machine, this software is programmed to look at a PCI port that the card is plugged into. i recently upgraded the box…
Giovanni
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Data bus error when using ioread32 in PCIE driver

I am developing a PCIE device driver for Openwrt, which is also a linux system. Here is a weird situation. After Initializing the driver in probe function, I can read(by ioread32) correct data (preset value:123456) from the buffer address obtained…
Woody Huang
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iMX6: MSI-X not working in Linux PCIe device driver

I'm trying to get MSI-X working on an iMX6 (Freescale/NXP/Qualcomm) CPU in Linux v4.1 for a PCIe character device driver. Whenever I call either pci_enable_msix() or pci_enable_msix_range() or pci_enable_msix_exact() I get an EINVAL value returned.…
user2205930
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Will my graphics card run at PCIE x8 or PCIE x15?

For example I have a 16 lane CPU, with a PCIE x16 graphics card and a PCIE x1 Wifi card. Does this make my graphics card run at PCIE x8 or PCIE x15? Edit: My CPU is a Intel Core i5 7600k, and my Motherboard is an MSI Mortar Z270.
Cameron K
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How to implement mmap for bar0

I'm trying to write my own Linux PCIe driver. I would like to write my mmap function so that it maps bar0, I realize I can do this without writing a driver but I'm doing this mostly for learning purposes. My first question is why would you need to…
Matthew
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Does it possible to reallocate PCIe BAR memory without restart or Hot-Plug (Windows-7 drivers related)

My PC has Win-7 Embedded and I'm trying to connect to PCIe switch BAR. At first when windows detects the PCIe switch it is not configured to use the requested BAR. After my program change the switch settings it is required to restart windows in…
Shai B.
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How to get linksta pcie in linux?

I'm coding in cpp, and I want to get back linksta whice is including number of lanes and bandwidth. I know I can get it with regex in lspci -vv, but I perfer an API if someone know any.
asaf
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How to measure latency between hardware interrupt and related system call?

I have a Linux machine with two PCIe RS-485 cards (XR17V354 & XR17V352). I have one port on one of the cards hardwired to one port on the other card. These cards are driven by the generic serial driver (serial8250). I am running a test and measuring…
bsirang
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device tree interrupt remapping for pcie and pci device

How to assign interrupt number in device tree for each pcie and pci devices connected to main host bridge via pcie switch and pcie-pci bridge ? Is it require to do it manually or it will automatically assigned ?
Savan
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Why is the max number of PCI lanes possible in your system set by your CPU? Even with DMA being widespread

There are a few scenarios I'm curious about: a transfer from GPU1 memory to GPU2 memory over the PCI bus a transfer from GPU1 to main memory with DMA a transfer from GPU1 to main memory without DMA Will all these scenarios be limited to the total…
randyrand
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Changing PCI address mapping to Fixed address

I am facing an issue in accessing BAR address that enumerated in Linux due to bug in my hardware(Address decoder). With enumerated Linux bar address if we access my device register from Linux host will result in garbage value, This is due to…
Selvan Mani
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Why did PCI Express suffer high latency in pipeline transfer mode?

I used the Arria V GX FPGA Starter Kit connected to a computer via PCI Express (PCIE). In the Kit, I implemented my Direct Memory Access (DMA) Read/Write using the pipeline transfer. The DMA read the data from the PC's memory then write to another…
Thuan N.
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Ordering of DMA reads and writes in PCI Express devices

Short version: I have two main questions: Are DMA writes allowed to pass DMA reads? If so, is there any way to stop them from doing so (e.g. by setting a flag, etc.)? Do DMA reads respect any byte-ordering? e.g. left-to-right, right-to-left, or is…
narengi
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