I'm getting the following error in ModelSim:
Error: [..]/test1_toVectorAlignment_rtl.vhd(40): Ambiguous type in infix expression; t_RAMXx8 or ieee.std_logic_1164.STD_LOGIC_VECTOR.
ARCHITECTURE rtl OF test1_toVectorAlignment IS
type t_RAMXx8 is array (natural RANGE <>) of std_logic_vector(7 downto 0);
signal RAM28x8: t_RAMXx8(0 to 27);
BEGIN
...
currentIq<=unsigned(RAM28x8(5)(4 downto 0) & RAM28x8(4));
...
END rtl;
Entity declaration:
ENTITY test1_toVectorAlignment IS
...
currentIq: out unsigned(12 downto 0);
...
END test1_toVectorAlignment;
Can someone tell me with this information how I can solve this problem?