VHDL integer range inclusive? Difference in FPGA vs. simulation

Question

I'm new to FPGAs. I've been doing some simple tests and I found an issue I don't fully understand.

I have a 50MHz clock source.

I have a signal defined as:

SIGNAL ledCounter : integer range 0 to 25000000 := 0;

When the ledCounter reaches 25,000,000 I toggle an LED and reset the counter. This works great directly on the FPGA.

IF (rising_edge(CLK)) THEN
    ledCounter <= ledCounter + 1;

    IF (ledCounter = 25000000) THEN
        ledCounter <= 0;
        toggle <= not toggle;
        LED(0) <= toggle;
    END IF;
END IF;

When running inside ModelSim I get an error when the counter reaches 25000000. For it to run in the simulator I have to define the range as:

SIGNAL ledCounter : integer range 0 to 25000001 := 0;

Does anyone have any insight into why this is happening? The code runs on the FPGA well but won't run in the simulator without the above modification.

EDIT: The modelsim error is nondescriptive: Cannot continue because of fatal error. HDL call sequence. Stopped at C:/Users/robert/Documents/fpga/testsim/test.vhd 20 Process line__17

Are you possibly attempting to increment the counter beyond 25000000 in your simulation? This will probably cause an out-of-bounds error in simulation, but may result in different behavior (such as wrap-around) in hardware. — Josh, Mar 11 '15 at 19:20
If you post the exact error you get from ModelSim, it will help folks answer your question more helpfully. (Most likely, you are somehow incrementing the counter out-of-bounds -- but that's just a guess based on personal experience without seeing the error message.) — wjl, Mar 11 '15 at 19:23
I updated the code to include the increment. It is a very simple program. I do not think I am incrementing beyond the limit. Also, on the FPGA the LED is successfully toggled when ledCounter = 25000000 so I am pretty sure there is no wraparound or anything happening. @Josh — RobC, Mar 11 '15 at 19:24

score 6 · Accepted Answer · answered Mar 11 '15 at 19:29

6

This happens because the line ledCounter <= ledCounter + 1 happens before the comparaison. Even if ledCounter's value won't actually reach 25000001, since overridden by the following statements, at this point it is scheduled to reach it, causing the simulation error. You can solve it easily by moving the increment in an else branch:

IF (rising_edge(CLK)) THEN
    IF (ledCounter = 25000000) THEN
        ledCounter <= 0;
        toggle <= not toggle;
        LED(0) <= toggle;
    ELSE
        ledCounter <= ledCounter + 1;
    END IF;
END IF;

That way, ledCounter is never scheduled to be 25000001 and no error will occur. Notice that both code behave exactly the same.

answered Mar 11 '15 at 19:29

Jonathan Drolet

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Thanks! That fixed the simulation. – RobC Mar 11 '15 at 19:52
2

IEEE Std 1076-2008, 10.5.2.2 Executing a simple assignment statement, para 6: "For the execution of a simple waveform assignment statement whose target is of a scalar type, the waveform on its right-hand side is first evaluated. ...It is also an error if the value of any value expression in the waveform does not belong to the subtype of the target." – Mar 11 '15 at 20:14

VHDL integer range inclusive? Difference in FPGA vs. simulation

1 Answers1