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Questions tagged [lattice-diamond]

Lattice Diamond is Lattice synthesis tool for newer devices.

Lattice Diamond is Lattice synthesis tool for newer devices.

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how to properly access the lattice MachX02 SRAM address with pointers

I am using the Lattice Mico8 Processor as my SoC processor, together with a UART and an SRAM. I am trying to create a software to talk to my Verilog code. For this, I am using a pointer to get values from the UART, store in an SRAM, and later…
Alex
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Lattice Diamond v 3.11 on Linux: problem with ftdio_sio

On Linux, since v3.11, it seems that Lattice Diamond can only detect a FTDI cable if the kernel driver ftdio_sio has been removed. On v3.10 and before, it was possible to just unbind the ftdi tty (ttyUSB*) with a udev rule (many blogs which explain…
gregoiregentil
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EBR block in Lattice Diamond

I have a MachXO3 chip. Family datasheet is available here: http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/MachXO23/DS1047-MachXO3-Family-Data-Sheet.pdf?document_id=50121 The datasheet says that EBR is composed of 9-kbit on page…
gregoiregentil
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VHDL design - creating if loop within second process not working

I've written a VHDL design that halves the clock's frequency and outputs this 'data clock' onto the sclk pin. I also have a data pin called 'sda' that I'd like to send data out of. The following code works fine. I see the clock signal out of sclk…
JJT
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lattice mackXO3 board output transient

I have a lattice MachXO3L starter kit and I'm having some trouble with inputs, I think. I'm tried reducing the code only to read 4 switches (MachXO3 Starter Kit User’s Guide page 26) and light 4 LEDs according to the state of the switch. The problem…
user169808
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Lattice Diamond `include not working

I am using Lattice Diamond and I have a verilog file with a bunch of `define statements to define global constants. I include this "header" file into another file. It finds the file but there is an error: " 2049990 ERROR -…
user2676271
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Lattice Diamond does not allow me to open Active-HDL, it shows me this message

(FLEXlm error = -5) No such feature exists. Please run the License Information of the Help menu to verify Aldec license environment settings or define new license. For ordering information contact sales@aldec.com I have downloaded the free version…
sujeto1
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Configuration of MAC IP core

How can we access configuration registers of Lattice Tri-Speed Ethernet MAC (TSMAC) IP Core in lattice diamond tool ?
Test
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Can anybody confirm, that Lattice Synthesis Engine does not correctly evaluate VHDL assert statements?

I'm using assert VHDL statements to check global constants and generic parameters in VHDL architectures, if they obey to the supported parameter set of a VHDL design. An always true assert statement is reported in the log. I think this is a…
Paebbels
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Missing signal names in Lattice Diamond

I have a Lattice Diamond project for an SPI multiplexer, which has the following module definition: module spimux ( input bmck, input bssel, input bmosi, output bmiso, input[3:0] a, output[13:0] mck, output[13:0] ssel, output[13:0] mosi, input[13:0]…
Dave
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Creating a time delay in Verilog that can be synthesized

I am attempting to create a time delay that will synthesize, and not just work in my simulation. The delay needs to be 1.439548 ms or as close as possible to that precision. I am using Lattice Diamond and a MACHX02 7000HE FPGA. The delay is used to…
user3780413
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Lattice Diamond 2.1

I upgraded my machine from WinXP to Win7, and at the same installed Lattice Diamond 3.1. My more complex simulations hang, Active-HDL uses 100% CPU time and is obviously in an infinite loop. Stupidly I don't have the installation of Lattice Diamond…
Francis Cagney
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How to access text files at synthesis level

I am writing Verilog code using Lattice Diamond for synthesis. I have binary data in a text file which I want to use as input for my code. At simulation level we can use $readmemb function to do it. How is this done at synthesis level? I want to…
Saad Rafey
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Errors during synthesis

I had written a Verilog code given below for simulation purpose.It is working properly during simulation. module read_1(clk,reset); input clk,reset; reg [0:23]dataout; reg htpv; reg [0:23]e_data; reg[1:24]data_out; reg…
Saad Rafey
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Warning "has no load", but I can't see why

I got these warnings from Lattice Diamond for each instance of any uart (currently 11) WARNING - ngdbuild: logical net 'UartGenerator_0_Uart_i/Uart/rxCounter_cry_14' has no load WARNING - ngdbuild: logical net…
jeb
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