how to properly access the lattice MachX02 SRAM address with pointers

Question

I am using the Lattice Mico8 Processor as my SoC processor, together with a UART and an SRAM. I am trying to create a software to talk to my Verilog code. For this, I am using a pointer to get values from the UART, store in an SRAM, and later retrieve in the hardware. I initialize the pointer with an address and increment as required. However, it seems the values I fetch from the UART never get stored in the SRAM addresses. I can't even print it back right after getting it, even when I apply a bit of delay. I tried to let the pointer point to another variable's address and with that, I can print back to the UART after getting it. Is there something I am doing wrong here? Or rather there is a problem with the SRAM. I have posted a tiny snippet of my code where I need help.

void My_Funt (MicoUartCtx_t *pUart, int *sramaddr)
{
    int loopvar;
    char rcvdChar;

    sramaddr =(int *)0x804;

    for ( loopvar =0;loopvar<7;loopvar++)
    {
        MicoUart_getC (pUart, &rcvdChar);

        if ( loopvar == 0 )
        {
            if ( ( rcvdChar == 0x2B)|( rcvdChar == 0x2D))
                ;
            else
            {
                SendString (pUart, WRNG_MSG_1);
                break;
            }
        }
        else if ( loopvar == 4 )
        {
            if (  rcvdChar != 0x2E)
            {
                SendString (pUart, WRNG_MSG_1);
                break;
            }
        }
        else if ( ( loopvar == 6 ) || ( loopvar == 7 ) )
        {
            if      ( rcvdChar == '\r')         break;
            else if ( ( (int)(rcvdChar) >= 48 )&&( (int)(rcvdChar) <= 57 ) )
                ;
            else
            {
                SendString (pUart, WRNG_MSG_1);
                break;
            }
        }
        else
        {
            if  ( ( (int)(rcvdChar) >= 48 )&&( (int)(rcvdChar) <= 57 ) )
                ;
            else
            {
                SendString (pUart, WRNG_MSG_1);
                break;
            }
        }

        if  ( rcvdChar == '\r')         break;

        *sramaddr = rcvdChar;
        MicoUart_putC (pUart, rcvdChar);
        MicoSleepMicroSecs (100)
        MicoUart_putC (pUart, (char) *sramaddr); // this line was edited to test if the value was retrievable from the SRAM
        sramaddr++;
    }

    sramaddr =(int *)0x810;
    *sramaddr = loopvar;
}

At least I expect the value to be put on the UART screen just to know that it is there in the SRAM. I tried to use the Lattice Reveal System to debug my code by setting the trigger as the SRAM's CS. That never triggers.

Just for my understanding: Why do you give the pointer `sramaddr` to `My_Funt()` if you overwrite it in the first assignment? — the busybee, Aug 27 '19 at 07:47
Now for the question: How do you define the RAM address in the FPGA configuration? Are you sure that it is at 0x804 and at least of size `8 * sizeof (int)` (and at 0x810 and size `sizeof (int)`)? How many bytes does an `int` take on your system? — the busybee, Aug 27 '19 at 07:50
That's just a fluke I had in the beginning. I will edit it out soon. — Alex, Aug 27 '19 at 07:50
@thebusybee First of all in this architecture, an int is 2Bytes. The hardware code (Verilog) accesses a portion of the SRAM on the FPGA whose address range is from 0x00000800 to 0x00000900. This range was specified in the Lattice software and the code got generated for me. So I am sure the address falls within the editable range of the ram. — Alex, Aug 27 '19 at 07:53
A super simple test: Write a program that fills some range with a detectable pattern, for example `(addr >> 8) + (addr & 0xFF)`. Then loop again over the range, read each byte, and send it through the UART. Instead of using library functions you could convert each byte into two characters by accessing `static const char hex[] = "0123456789ABCDEF";` using each 4 bit part as index. This way you can make sure that the RAM is accessible and/or existing at all. Your development system should also provide some debugging capabilities to "look into" the logic blocks. — the busybee, Aug 27 '19 at 08:05

how to properly access the lattice MachX02 SRAM address with pointers

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