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I am attempting to create a time delay that will synthesize, and not just work in my simulation. The delay needs to be 1.439548 ms or as close as possible to that precision. I am using Lattice Diamond and a MACHX02 7000HE FPGA. The delay is used to wait the specified time required between data transactions. So far I am using an internal oscillator to run a separate counter which is used to spit out my data one bit at a time at the specified time intervals (using 2.15Mhz at 38400 baud). Do I need to use another clock/counter for my delay? If so, is anyone familiar with how to define and use a clock with this board? I am very confused and this is the last requirement for my program. Any help is appreciated.

Paebbels
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user3780413
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  • Why don't you use another counter that uses 2.15Mhz clock to create a delay of `1.439548 ms`? – Ari Jun 26 '14 at 18:04
  • possible duplicate of [How to include time delay in synthesized verilog?](http://stackoverflow.com/questions/17361606/how-to-include-time-delay-in-synthesized-verilog) – Qiu Jun 26 '14 at 18:16

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Used internal oscillator and counter to get the right time delay. Counter value was determined by time required to output my 40 data bits at the 2.15 MHz frequency.

user3780413
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