Lattice Diamond is Lattice synthesis tool for newer devices.
Lattice Diamond is Lattice synthesis tool for newer devices.
Questions tagged [lattice-diamond]
47 questions
1
vote
1 answer
FPGA IO configuration: Effect of weak pull up/down on an output
What is the effect of configuring a pull mode on a pin designated as output in the synthesis?
Does the pull mode still take effect?
Is its use only apparent if we set the output to tristate?
See the example below with a Lattice Diamond tool, I am…
CJC
- 795
- 8
- 25
1
vote
1 answer
MachX03 library error in Active-hdl for fpga simulation
edit: I just reinstalled lattice diamond and the updates, Active-hdl was installed automatically, but the simulation still gives me the same error. when i change library machXO3; use machXO3.all; to library machXO2; use machXO2.all; it…
user169808
- 503
- 1
- 6
- 27
1
vote
0 answers
vhdl tristate output in lattice diamond
i'm trying to write a module to read/write to a sram ic (CY7C1011CV33 -10ns), but I'm having a hard time outputting something to the inout port. I was able to make things work close enough to how I want, but now I have a different problem. When I…
user169808
- 503
- 1
- 6
- 27
1
vote
2 answers
Llattice diamond programmer-tool
install Lattice Diamond 3.10 on my computer with Manjaro 17.1 and everything works correctly just because of a problem. The programming tool does not work, when I try to execute it I get a window with a message:
"can not load library:
…
Cristian Piste
- 23
- 7
1
vote
1 answer
VHDL - "Net pwr is constantly driven"
I am attempting to learn VHDL and as an exercise I am trying to construct a very simple serial port that uses RS-232 style signalling (8N1 format).
Here's the code for both of the vhdl files in the small project...
"glue.vhd"... (top level…
user5069935
1
vote
0 answers
Lattice Diamond: Found inferred clock
I am working on a project for a class and I ran into to problem. My task is to draw a registry scheme. I did so but I get warning and my test results are wrong. The warning that I get is :
2019993 WARNING - MT420 |Found inferred clock SCHEMA1|C…
zerociudo
- 357
- 8
- 25
1
vote
0 answers
code to read device ID of MachXo2 with FTDI -JTAG
In my project I am working on MachX02 programming with FTDI master using JTAG functionality. I am trying to read device ID of MachX02, but not working, here is my sample code to read device ID of MachX02:
cmd_buffer[0] = 0xE0;
cmd_buffer[1] =…
Maggyrock
- 11
- 2
1
vote
1 answer
How does Lattice Diamond map initial RAM values to the EBR primitives?
I'm reading initial RAM values for a 4 KiB (1Ki x 32-Bit) True-Dual-Port RAM from disk. Because my Lattice ECP5 devices has only 18-bit wide Embedded Block RAMs (EBRs), 2 RAMs are combined to match the word size of 32 bit.
My ocram.mem file has 4…
Paebbels
- 15,573
- 13
- 70
- 139
0
votes
1 answer
(VHDL-1154) near 'std_logic_vector' ; type conversion expects one single argument
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.ALL;
use ieee.math_real.all;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
port
(
signal Led_7 : out std_logic := '1';
signal Led_6 …
Keith Beech Hall
- 1
- 1
0
votes
0 answers
Lattice Diamond programmer, FPGA wont load from flash on power cycle
We have a design that has worked for years when programming with the Diamond WIn7 software. We are using the Advanced FPGA loader feature of the Diamond programming software in WIN10(v.3.12) now. We program the CPLD (LCMXO2-640ZE)with our .JED…
smcmurphy
- 1
- 1
0
votes
1 answer
Why doesn't Lattice Diamond use the sdc file?
I have inherited a Lattice Diamond project. Things seem to be fine, excpet for the systems constraints file. In the Lattice Diamon file list, the sdc file I have shows as greyed out.
Right clicking provides a menu with "set as active", however that…
Puffafish
- 111
- 2
0
votes
1 answer
FPGA Timing Closure: How to constraint path between 2 clocks or how to force a hold on a path?
In a Lattice Verilog FPGA design, I have two PLL-generated clocks at the same frequency 125MHz (8ns) but the second clock is at 90° shift of the first clock:
wire clk;
wire clk90; //clk90 is clk with phase at 90°
pllm pllm_inst(.CLKI(oscInternal),…
gregoiregentil
- 1,793
- 1
- 26
- 56
0
votes
1 answer
Diamond/ModelSim post-route timing simulation problems
I’m new to TinyFPGA, so I need a little help!
I’m working on a Tiny FPGA project for sensors and actuators where each tinyFPGA provides an 8 bit digital sensor input, and a 4 actuators output with different modes of operation (on/off, PWM, and…
Jonas
- 1
0
votes
1 answer
VHDL, error message; has multiple drivers
Im creating an Alu, these is my code.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is port (
entrada: in std_logic_vector(11 downto 0);
S: in std_logic_vector(3 downto 0);
load : in std_logic;
…
Alessia Houston
- 9
- 4
0
votes
1 answer
UART Transmitter only functions when embedded logic analyzer is running
I have been trying to implement a UART in order to communicate between my Lattice MachXO3D board and my computer. At the moment I am attempting to implement the transmission from the FPGA.
Upon testing on the hardware, I encountered a very strange…
Francisco Ayala Le Brun
- 3
- 1
- 2