0

I'm using assert VHDL statements to check global constants and generic parameters in VHDL architectures, if they obey to the supported parameter set of a VHDL design.

An always true assert statement is reported in the log. I think this is a bug.
Example: assert TRUE report "This should not be visible in the LSE log." severity NOTE;

Here is the complete test example:

library IEEE;
use     IEEE.std_logic_1164.all;
use     IEEE.numeric_std.all;

entity assert_test is
end entity;

architecture rtl of assert_test is
  type T_VENDOR is (VENDOR_ALTERA, VENDOR_LATTICE, VENDOR_XILINX);
  constant VENDOR  : T_VENDOR  := VENDOR_LATTICE;
begin -- line 39
  assert TRUE report "This should not be visible in the LSE log." severity NOTE;

  genInfer : if ((VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX)) generate
    assert FALSE report "Inside genInfer" severity NOTE;
  end generate;
  genAltera : if (VENDOR = VENDOR_ALTERA) generate
    assert FALSE report "Inside genAltera" severity NOTE;
  end generate;
  -- line 48
  assert ((VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX))
    report "Vendor '" & T_VENDOR'image(VENDOR) & "' not yet supported."
    severity failure;
  -- line 52
  -- workaround
  genAssert : if (not ((VENDOR = VENDOR_ALTERA) or (VENDOR = VENDOR_LATTICE) or (VENDOR = VENDOR_XILINX))) generate
    assert FALSE report "Vendor '" & T_VENDOR'image(VENDOR) & "' not yet supported." severity failure;
  end generate;
end architecture;

Here is my LSE log:

INFO - synthesis: d:/.../assert_test.vhdl(40): Found User declared VHDL assert of type Note: "This should not be visible in the LSE log.". VHDL-1700
INFO - synthesis: d:/.../assert_test.vhdl(43): Found User declared VHDL assert of type Note: "Inside genInfer". VHDL-1700
INFO - synthesis: d:/.../assert_test.vhdl(51): Found User declared VHDL assert of type Failure: "Vendor 'vendor_lattice' not yet supported.". VHDL-1700 Top module name (VHDL): assert_test

  • Can anyone confim this behavior?
  • It's a bug, isn't it?

Workaround:
Placing the assert statements into a generate statements, works as a workaround.

Paebbels
  • 15,573
  • 13
  • 70
  • 139
  • I think you're seeing an INFO that there's an ASSERT statement in the code, rather than an actual ASSERT. Which is ... not very useful! But I don't know that it's technically a bug... –  Dec 21 '15 at 15:35
  • But when it's "seeing" an assert statement, why is the one in the generate block not visible in the log? OK it's not 'generated', ... I think know what I mean ... :) As far as I can see, all assert and report statements are logged as an `INFO:` regardless of the severity value. The severity level is logged in a later text column for ex. `assert of type Failure: "My text ..."` – Paebbels Dec 21 '15 at 15:45
  • Concurrent assertion statements in an architecture were required to be supported by IEEE Std 1076.6-2004 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis (rescinded). I'd agree with Brian. As to why no INFO inside generate statements, can you distinguish between analysis and elaboration in your Lattice tool? –  Dec 21 '15 at 16:57
  • So if I understand you, a later stage of the process does run the asserts that actually trigger. So `assert false` should appear there, but not `assert true`. –  Dec 21 '15 at 16:57
  • There are no messages from analyze in the step. When I run synthesize (LSE), the report from above is shown. Yes `assert TRUE ...` should not appear in the log. It's a short test for my complex `VENDOR` test. The message says: *Vendor 'vendor_lattice' not yet supported*. So VENDOR is set to `VENDOR_LATTICE` and thus the complete condition must be true and the message should not be shown in the log. – Paebbels Dec 21 '15 at 17:17

0 Answers0