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I am using Quatus 2 Prime 16.1 Lite version.
what i am trying to do as follows, I have compiled float_pkg_c,fixed_pkg_c under ieee_proposed library as in shown in below link in comment. and i am using to_float to convert real variable to std logic vector as follows,

phi_c <= to_std_logic_vector( to_float(phi_c_F, float32'high, -float32'low) );

below phi_c_F is a variable which is to be calculated using sin, arcsin of math_real library.and i found operators in math_real non-synthesize, and i want there xx.dddddddd at least 10 decimal points. then, phi_c is send via Avalon memory mapping (32bits std logic vector) to HPS system.

in below code pre_digital,rp are integers and are signals which calculates in another process.

library ieee;
library ieee_proposed;
USE ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.STD_LOGIC_ARITH.ALL;
use ieee.STD_LOGIC_UNSIGNED.ALL;
use ieee_proposed.float_pkg.ALL;
use ieee_proposed.fixed_pkg.ALL;
use ieee_proposed.fixed_float_types.ALL;

inside architecture, 

PROCESS(clk_50,start_cal)
variable Pr_F,rp_rad_s_F,F_c_F,ph_c_F,t_p_F,l_c_F,r_c_F,Ar_F,pre_R ,r_s: float (4 downto -27); 
BEGIN
--r_s := 8.98;
--r_c_F := 3.44;
--l_c_F := 5.67;
IF rising_edge(clk_50)  AND start_cal ='1'  THEN

pre_R           := to_float(pre_digital,4 ,27) ;       
Pr_F            := 3.3 * (pre_R / 65535.0);    
rpm_rad_s_F     := to_float(rp,4 ,27) * (2.0 * MATH_PI / 60.0);
Ar_F            := MATH_PI*r_s*r_s;
F_c_F           := Pr_F * Ar_F;             
ph_c_F          := arcsin((r_c_F / l_c_F) * sin(rp_rad_s_F *  to_float(t,4 ,27)));

ph_c_F_vctr  <= to_std_logic_vector(ph_c_F);
END IF;
END PROCESS;

when compiling soc.system i get error,

Error (10511): VHDL Qualified Expression error at test_pipe.vhd(136): ARCSIN type specified in Qualified Expression must match UNRESOLVED_float type that is implied for expression by context

iopertyki
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  • [Does the Quartus Prime software support IEEE fixed_pkg and float_pkg libraries in VHDL-2008?](https://www.altera.com/support/support-resources/knowledge-base/solutions/rd09062016_335.html) It also begs the question as to why you are trying to include floating point in a UART. –  Jun 26 '17 at 17:04
  • https://stackoverflow.com/questions/19580207/compiling-vhdl-into-a-library-using-altera-quartus-ii this link shows everything that i needed thank you – iopertyki Jun 26 '17 at 17:11
  • @user1155120 then the method in above link will not let me do calculations with floating numbers in Quartus 16.1 Lite version ? I need to use floating numbers with sin, cos in math_real library. – iopertyki Jun 26 '17 at 23:58
  • Please explain your problem: what do you want to achieve? Why do you need floating point arithmetic and in what way? Show some code maybe. Floating point in FPGA is a very big challenge and a very inefficient use of resources. Why are you using an FPGA for this? – JHBonarius Jun 27 '17 at 11:38
  • @JHBonarius i have added the vdhl code that I need to run on soc-fpga – iopertyki Jun 28 '17 at 05:03
  • I was just looking back at your edits. Please don't radically change/edit your question each time. My a new question for each new question. – JHBonarius Jun 28 '17 at 15:13
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    And why are you using `std_logic_arith`? It is a bad package. You should only use `numeric_std`. – JHBonarius Jun 28 '17 at 15:15
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    I have to agree with @JHBonarius - you seem to be attempting something that is very hard, when this line of code - `IF rising_edge(clk_50) AND start_cal ='1' THEN` - suggests you are a beginner. Why are you trying to do this? – Matthew Taylor Jun 29 '17 at 10:28
  • I need to implement this on hardware level (VHDL) for my project. – iopertyki Jun 29 '17 at 11:19
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    Do you really need floating point? I have been designing digital hardware for receiving radio signals on and off for 28 years. There is quite a big dynamic range requirement - many 10s of dB, yet I have never needed floating point. Could you use fixed point? – Matthew Taylor Jun 29 '17 at 12:42
  • @Matthew Taylor yes i can use fixed point. I cannot drop all decimal points. I found arcsin in ALTERA_FP_FUNCTIONS IP core. this can be used here?right? – iopertyki Jun 29 '17 at 13:00
  • I don't know. I have never used Altera IP. – Matthew Taylor Jun 29 '17 at 13:11
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    From what I can see, ALTERA_FP_FUNCTIONS is for Arria 10, whilst your board has a Cyclone 5 on it. – Matthew Taylor Jun 29 '17 at 14:58
  • @Matthew Taylor then there is no other way to get arcsin? instead of making cordic ip or a lookup table for arcsin – iopertyki Jun 29 '17 at 15:01
  • Of course it is possible. It is just very complex. People get paid big bucks to design that kind of stuff. – JHBonarius Jun 29 '17 at 17:45

1 Answers1

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Judging by your code and requirements, it seems you are not aware of the capabilities of an FPGA. An FPGA consist of a collection of programmable logic lookup tables, combined with some hardwired multipliers. Except for the newest generation Altera (Stratix 10 e.g.), these multipliers are fixed-point only and would require extra logic in the LUTs to realize floating-point kind of operations. Also, the multipliers only offer limited precision: ~18 bit.

You seem to want full floating point precision (64 bit) and perform very complex operations, as division and trigonometric functions (sin/arcsin). A lot of logic is required to realize these functions. Trigonometric functions are not even implemented in the float_pkg library. You will probably have to use a CORDIC-like component to realize such a function.

But just think about what you seem to want to achieve in your code:

  • 2 * floating-point division
  • 8 * floating-point multiplication
  • 1 * sin()
  • 1 * arcsin()

All within one clock cycle! clk_50 seems to indicate 50 MHz... That's not going to work. You need to pipeline it properly.

What you want to realize on your FPGA is advanced stuff. You really need to know what you are doing. Please start simple, by flashing a LED or something.

Likely you should just run this code on a general purpose processor and not use an FPGA...

JHBonarius
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  • Yes I am new to perform this type of mathematical functions on fpga. Is there any standard sin, cos, tan lookup table for Altera that can be used in De0 nano Soc board? and what is CORDIC component? can you show a link here for CORDIC vhdl file. – iopertyki Jun 28 '17 at 15:54
  • I have never done sin arcsin functions in VHDL, so this is hard for me, if you can direct me to a source i will manage myself. – iopertyki Jun 28 '17 at 16:19
  • @iopertyki please do some research yourself. just Google "CORDIC" for instance. This is very complex hardware design; it cannot be explained by a simple link. – JHBonarius Jun 29 '17 at 09:47
  • is this same for the verilog? – iopertyki Jun 29 '17 at 11:46
  • @iopertyki what do you think the difference between verilog and VHDL is? You should really do some research yourself before asking questions. – JHBonarius Jun 29 '17 at 12:00
  • ALTERA_FP_FUNCTIONS IP core can be used in my work isn't it? it has arcsin, arccos – iopertyki Jun 29 '17 at 12:18
  • I only see sine, cosine and arctangent in the IP user guide. But anyhow, why are you asking this? I don't know if you can use it. I don't know what your requirements are, nor your capabilities as a designer. – JHBonarius Jun 29 '17 at 17:44