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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Instruction Set Encoding

I'm trying to solve this exercise : You will encode an Instruction Set for a processor with 32 registers (R0-R31). The arithmetic-logical instructions are in the form : Ri<-Rj op Rk and there are 22 bits available for their encoding…
IrishDog
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Theory regarding jump functions?

In an ISA of type MIPS,there are two types of addressing for the functions Branch and Jump.These are PC-relative and pseudodirect.I want to know why do we use two different ways of addressing for two types of instructions? is this…
user3210269
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Division of double word in MASM

HDIVIDEND DW 1234H LDIVIDEND DW 5678H DIVISOR DW 1234H MOV AX,LDIVIDEND MOV DX,HDIVIDEND DIV DIVISOR I am getting an "Illeagal instruction" on running a masm code at the instruction DIV DIVISOR Where HDIVIDEND is the higher order bytes of…
user3041058
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What java command/binary uses for printing out the readable java bytecode?

I try to print out the readable java bytecode to see the monitorenter and monitorexit to study about the deadlock and synchronization instruction set but I don't know what the java command or binary that I should use to get the readable java…
user2342262
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Multiply using addition and a restricted set of instructions

I am building a CPU circuit with Logisim. My CPU has only 2 general purpose registers and a 16-byte RAM. I have encoded the following instruction set (Rxy means one of the two registers) • ADD Rxy, Rxy (add Rxy and Rxy and store result inside the…
Justin D.
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integer and float instructions in sparc

While working with SPARC-V9 instruction set, I am trying to classify some instructions as Integer or Float. I want to know do we categorize branch instructions as integer? What about NOP? What about load/store? Another issue is, when I see LDF …
mahmood
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movq and 64 bit numbers

When I write to a register, everything is fine, movq $0xffffffffffffffff, %rax But I get Error: operand size mismatch when I write to a memory location, movq $0xffffffffffffffff, -8(%rbp) Why is that? I see in compiled C code that in asm these…
ericj
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Register Operands in MIPS

I'm trying to learn MIPS and I've encountered the following example that shows how to convert a C code to MIPS: I don't understand what is the purpose of the third MIPS line. Isn't the lw operand simply copies the value from t1 to t0 ?
Robert777
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Is it possible that in MIPS an instruction's certain steps come before that of its predecessor in a pipelined structure?

This is a problem about computer architecture and hope somebody has a clue. More specifically, it is about MIPS instruction pipelined flow. But I feel obscured about some aspects of it. Because I currently do not have enough reputation so I cannot…
smilingdays
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MIPS register instruction decoding

I've decode the three MIPS registries under here, but I'm not sure if I'm applying the theory correctly. Could someone confirm my answers and perhaps shed some light on decoding the first address? 0010 34422345 ori $2 , $2 ,0 x2345 0018 24020007 li…
Anshin
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When a gcc application is compiled in release mode (O3) what instruction set extensions are used?

When a GNU C / C++ application is compiled in vanilla release mode (O3) what instruction set extensions are used? How do the extended instruction set come into play? Are multiple code blocks included in the resulting executable and then used if…
JeffV
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Assembly Language, what exactly is a specialized instruction?

I'm currently studying for a Assembly Language Exam and have come across this question in a past paper, In assembly what is meant by a specialized instruction? Give an example of one. How does a CPU designer decide which instruction to …
Bungalo Soldier
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What is the difference between x86 assembly and other versions of assembly?

I understand that there are many versions of the assembly programming language, such as x86, ARM, MIPS, Motorola, etc... which run on various architectures. However, why is this? How does assembly work? Why is it that I can't use one version of…
user1800989
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CPU instruction sets for linear algebra?

I'm in a situation where I have to perform some linear algebra calculations with a matrix that almost never changes and a lot of small vectors ( very very few 3x3 or 4x4 matrices and vectors with 3 values ) in C++, I was thinking about using some…
user2485710
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In ARMv7, which special cases indicate that an encoding does not apply?

I am reading the ARMv7 architecture reference manual in order to implement a arm disassembler. In the annexe P.2.1 about the pseudo code, page 2644, it is written : "If there are multiple matching encoding diagrams [matching for an instruction], all…
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