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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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MIPS Register file size given opcode and register sizes

I have been given a simple ISA with two registers. opcode: 2 bits, register1: 3 bits, register2: 3 bits. It is asking me to find the size of the register file, how many registers can be addressed, and If each register’s size is the same that the…
JuiCe
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How to read ISA disassembly? Also GPU-Pipelining and Wait states

I'm trying to understand what machine code the OpenCL compiler produces in order to optimize it. Therefore I used the tool m2s-opencl-kc (from multi2sim) to offline-compile my *.cl file and keep intermediate files (switch: -a) as the *.isa file.…
SDwarfs
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Designing ALU Control block for single cycle MIPS

Hope this isn't off topic for Stack Overflow. I was learning about MIPS and I've gotten stuck at this step. This is the truth table for the ALU Control Block. Now this is the first time I'm coming across such a complicated truth table with don't…
user1265125
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using ISA to expose an internal MVC website

We have an internal server running an MVC3 application, which has been made available on our external server by using an ISA server. However; it is not applying the CSS, as the references to the external site are not mapped correctly. The main…
Luke Duddridge
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JVM instruction set CPU cycles & byte size

The Java Virtual Machine Instruction Set page provides information about mnemonics such as aaload, aastore... etc. However neither the cpu cycles that these mnemonics would take up is mentioned nor is there any info on the byte size or word size of…
Kevin Boyd
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Returning from ARM7 nested subroutine

Ok, I am trying to implement the selection sort algorithm in ARM7 Assembly. It starts with last element of array and works its way down to first element. It works for the first swap, but then exits before continuing on. I talked to my professor and…
vt-cwalker
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Homework in assembly language

I have this simple code in assembly: 1000 Add R3,R2,#20 1004 Susbtract R5,R4,#3 1008 And R6,R3,#0x3A 1012 Add R7,R2,R4 My question is what does the "And" do... I am really confused about it, I am doing my homework and I'm…
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In MIPS can an I-Type instruction cause a hazard?

I know that consecutive R-Type instructions can cause a hazard, for example: add $2, $2, $1 add $2, $2, $3 but can consecutive I-Type instructions? For example: addi $2, $0, 10 addi $2, $0, 5
Jason Pather
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the set of all bit patterns that can be placed in a desired register using a single instruction

Given the following set of MiniMIPS instructions: Load upper immediate Add Subtract Set less than Add immediate Set less than immediate Add OR XOR NOR AND immediate OR immediate XOR immediate Load word Store word In MiniMips instructions, It's…
Traveling Salesman
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how to allocate an 128 bit array with new Intel instructions with dynamic memory?

I am new working with new Intel instructions, so until now I just had been working with static memory, so I have a declaration as: __m128i pResult[10]; But now I am wondering if it is possible to allocate the memory in a dynamic way, as using…
user1462592
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How does arm svc instruction works?

How does SVC (SWI) instruction works? Where it puts supevisor call id and other data? Where to get a list of all supervisor call ids, its parameters and return types? Im tried to find that all in google but it shows only useless things and nothing…
TX3
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Pushing the AL register in x86 assembly

I am making my own OS in 16 bits x86 assembly with NASM and in one part of the code I have to push the AL register to the stack. But when I do push al I just says: firstos.asm:127: error: invalid combination of opcode and operands I also tried…
phasmida
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Is there a flag register in the Power ISA?

Is there a flag register in the Power ISA, similar to EFLAGS in the x86 machines? It could have some other name, for example it could be called "Status Register" or something of that kind, but its purpose would be saving some general attributes of…
JSpruce
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How to switch from different instructions/rules in an elegant way

hoping for your help! I'm doing a java project that reproduces the logo language and im capped as I can't find an elegant and not too complicated way to switch between different rules / instructions, the project focuses on advanced programming and…
anthony eleuteri
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how does the SUB instruction work in assembly AVR

how does the SUB instruction work in AVR assembly? does it take the twos compliment and add it or does it function differently? If I subtract two 8- bit numbers, say 1 - 2 and the answer is -1, should I expect the twos complement of 1 or some other…
Tzanker
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