Instruction Set Encoding

Question

I'm trying to solve this exercise :

You will encode an Instruction Set for a processor with 32 registers (R0-R31). The arithmetic-logical instructions are in the form :

Ri<-Rj op Rk

and there are 22 bits available for their encoding .

Reading-Writing instructions are in the form :

Ri<-memory[Rj+offset] (i,j = 0...31)
Ri->memory[Rj+offset] (i,j = 0...31)

and there are 30 bits available for their encoding .

i) How many arithmetical-logical instructions can you encode ? ii) Calculate the offset's max length in bits .

I tried to find solutions , been searching for hours but didn't find anything. Any help would be awesome!

If you've been trying for hours, why not summarize what you came up with? — Leeor, Jan 27 '14 at 10:20
Because I didn't find any specific solution or something that could help. — IrishDog, Jan 27 '14 at 11:17

score 1 · Answer 1 · answered Feb 21 '14 at 12:30

If you have 32 registers in your ISA, then you know how much space each register specifier takes up (5bits each). The remaining bits left over can be used for specifying the specific type of instruction ("opcode") and the immediate ("offset", in the case of the ld/st instructions).

The register/register instruction requires 3 specifiers, so that's 15 bits. The remaining bits can all go to specifying the type of instruction.

Instruction Set Encoding

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