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I need to learn about accumulator machines, but there is next to nothing written about them. Computer architecture channels seem to be flooded with general-purpose register ISAs (like MIPS, x86, etc).

I know that accumulator machines only have one register (called the Accumulator Register) that is implicit and not specified in any of the operations. In general, an instruction for an accumulator architecture is supposed to look something like: add memaddress.

However, I need to get more specfic. I need to know exactly how many bits are in the various instruction fields (i.e. opcode) for an instruction of an accumulator machine.

I have the following accumulator machine:

  • 2^24 words of memory (words are 32-bits wide)
  • Fixed format instruction (but how many bits??)
  • A 32-bit accumulator register
  • An index register X
  • Index addressing mode: address field + X when indexing is indicated in the instruction
  • Capable of performing a total of 128 operations

The last bullet tells me that the opcode of an instruction would be 7 bits since 2^7=128.

What would the instruction format be for a load/store instruction vs. an arithmetic instruction like add? It would help greatly if I knew how many bits the fixed format instruction should be.

Peter Cordes
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jshapy8
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    There are tons of accumulator-architecture MCUs nowadays, like PIC and 8051. Besides there's no need for fixed-width instruction or fixed-width opcode. For example x86 has extensions and MIPS has the function field for increasing opcode space, so you don't necessarily need 7 bits for 128 instructions – phuclv Jan 24 '18 at 07:59
  • But x86 and MIPS aren't accumulator ISAs. Plus the MIPS `funct` field is for variations on an operation, but the *number* of operations should be 2^7=128 regarless of any present `funct` field – jshapy8 Jan 24 '18 at 20:53
  • I'm just giving them as example for the *unnecessary of having a fixed 7-bit opcode*, not that they're accumulator architecture (actually in some sense the 8086 has AX as the accumulator). For example there may be some common operators that need only 4 bits of opcode, with some reserved 4-bit values to indicate other less commonly used instructions, which need more than 7 bits for the opcode. In MIPS you have theoretically 2^12 instructions if all are of type-R, not 2^7 – phuclv Jan 25 '18 at 02:48
  • you may look at [PIC 12/13/14/16-bit instruction set](https://en.wikipedia.org/wiki/PIC_instruction_listings) for some inspiration – phuclv Jan 25 '18 at 03:08
  • *seem to be flooded with general-purpose register ISAs* - yes, because registers are fast and compact to address in machine code. Memory (even L1d cache) is relatively slow, and memory-indirect addressing (load a pointer then deref it) is clunky. Real code needs pointers in registers, and doesn't want to have to spill/reload constantly. If you're going to have 32-bit registers, it makes little sense to only have 1 of them, and bloat most instructions with an absolute address. – Peter Cordes Jun 24 '20 at 18:47

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