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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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AMD CPU Instruction Set

There is an AES instruction or a DRNG instruction of the Intel CPU. I would like to know if there is such an instruction on the AMD CPU or similar command. Or is there a web site where i can get information about this?
KIYOUNG KIM
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Sign Extended Instruction for PIC24

How you can implement the Sign Extended Instruction in VHDL (in ALU) for PIC24? I need to implement the following instructions and I don't have any idea how to implement SE. LOOP: mov 0x1020, w1 ; INW0=ff7f mov 0x1022, w2 ; INW1=8001 ior…
Andreea Dumitru
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Compilers and Instruction sets

"C is a genereal purpose language, not tied to a particular system" The C programming Language, BRIAN W KERNIGHAN & DENNIS M. RITCHIE Yet with the right compiler we can make a .exe which runs on every Windows machine, which in turn means on…
Nalda Oudas
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Is the following hypothetical instruction set Turing complete?

I have devised a hypothetical instruction set that I believe is Turing-complete. I cannot think of any computational operation that this instruction set is not able to complete. I would just like to verify that this hypothetical instruction set is…
Uncreative Name
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ARM Assembly TBB Instruction - how does jumping work?

so I'm trying to understand how TBB works for switch statements in Assembly. I see how it's written in the textbook/online manual, but I don't understand how the offsets work in the branch table. How does it go from branch table to instruction? How…
Fua
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Possible to mul r1,r1?

If I have movmr x,r1 Is it possible to do? mul r1,r1 As in (x*x). I'm trying to efficiently do this to save bytes but this is the best possible solution I can think of so far and can't seem to find if it's allowed. The whole equation is…
Lawdevo
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RISC-V: S-format instructions table

I have this table of S-format instructions. Can you explain to me what imm[11:5] and funct3 are? I know funct indicates its size in bits and sometimes it is 000 or 010. I don't know exactly why it's there. Also, imm[11:5] is also 7-bits of all…
James
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Difference between instruction sets

I'm trying to understand computer architecture and instructions set,but most of the material is rather cryptic, so I want to know: What is the difference between RISC/CISC and x86? What instruction set do modern intel CPUs use? I've been told that…
Trey
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Optimization of mov instruction based on ARM architecture

I'm graduate student in Korea and interested in the optimization eliminating mov instruction during compile time. Especially, in ARM ISA, I have observed that the mov instruction is used to handle stack operation (push or pop) and PC address…
Shumin Lee
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Compiler for RISC-V vector code generation

Is there a compiler available which generates the vector instructions according to the new vector extension proposed in RISC-V ISA specification v2.2?
kchanuec
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Little Man Computer : if(value==0){ some_statements;

I'm personally attempting to learn the little man computer. I found a problem: Write an LMC (Little Man Computer) program to do the following task. if (value == 0) { some_statements; } next_statement; My current answer: 00 901 IN…
JohnSmith1999
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Instructions per sec for Operating systems

I am new to Computer Architecture and Design. My question was a high level program Instruction set are executed in CPU one after another. Does it even involve Operating System instructions as overhead when executing these instructions ?. For…
Carbonizer
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Given a ROM dump file, how do I reverse engineer it to determine the CPU it runs on?

I recently bought a Sharp EL-9950 graphing calculator (which is considerably rare compared to the other brands). I have a copy of its OS upgrade file, which is essentially ROM dump for the new version (or at least I think it is). I searched…
Kyle Alexander Buan
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Why cannot push 8-byte immediate value on stack in x86-64?

I'm trying to understand x86-64 assembly and today I came across the following: I can do something like this: mov $0x74786574656d6f73, %rax #compiles to movabs push %rax While i can't do the following: push $0x74786574656d6f73 #8-byte I'm getting…
agienka
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how can I know number of instruction access?

I'm studying computer architecture. I'm confused about some quiz. when executing n instructions in load-store arch. lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 48($s3) then what is number of memory access, and number of instruction access? I think num…
SUN
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