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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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How do I know whether I'm looking at a CISC or RISC instruction set?

Is there any header present reliably across all "standard" (assuming its designed to be executed normally through some common computing platform) executable binaries that I can use to identify whether I'm looking at a CISC or RISC instruction…
J.Todd
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Why can't 16-bit instructions access the high registers of the general purpose registers

So right now I read the "Definitive Guide to ARM Cortex-M3/M4" book and can't understand why the 16-bit instructions cannot access the high general purpose registers R8-R12. It says that very few of them actually can access these registers but…
moonraccoon
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How comparison operator utilizes CPU cycle in programming

If I have following conditions then which comparison condition executes fast(in terms of CPU cycles and time): if(1 < 2) if(1 < 100)
dev2
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java.lang.verify error : Inconsistent stack height 1 != 2

I have a custom application in which we have generated the Java Instruction code.We are generating the code using javacc. In one of the Scenarios, we are getting java.lang.verify error : Inconsistent stack height 1 != 2 I checked the generated class…
Ashu
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i am searching a table that contains all instructions' full name in ISA

could anyone give me a link to the full name of the instructions in ISA? for example, the full name of the JAL is jump to link. i search for google but i can't find something like a table which could include all of them. Thanks!
C Lei
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simple pipelining and superscalar architecture

consider this instruction flow diagram.... instruction fetch->instruction decode->operands fetch->instruction execute->write back suppose a processor that supports both cisc and risc...like intel 486 now if we issue a risc instruction it takes…
AvinashK
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Max number of words to jump over in the PC-relative addressing mode

I'm reading a book of David Patterson and John Hennesy titled: Computer Organization and Design. In the RISC-V architecture set which the book is about there are two instruction formats related to jumping - SB-type and UJ-type. The former uses…
E. Shcherbo
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Extend risc-v instructions on QEMU

I want to extend the QEMU TCG (tiny code generator) to accept new instructions for the risc-v guest on my x86 machine. However, I have no experience on how the TCG works, so I was wondering if someone can give me some useful pointers on where to…
John
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what happens if the destination address j jumps to is an immediate value?

3. Mr.Noob is pondering about this strange line of MIPS instruction in his program: beq $t3, $t9, 0 #0 is the immediate value Which of the following statements is TRUE? A. That instruction is an “infinite loop”. B. That instruction can be removed…
lee chong wei
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Did the first compiler "writer" know x86 machine codes?

I'm sorry I'm new to this. Did the first compiler writer, for example the C compiler, knew all of intel x86 machine instructions. I'm asking because, some compilers compile source code to the processor's machine instructions right? So the compiler…
Nex
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how does CF(Carry flag) get set according to the computation t = a-b where a and b are unsigned integers

I'm new to x64-64, just a question on how does CF get set? I was reading a textbook which says: CF: Carry flag is used when most recent operation generated a carry out of the most significant bit. Used to detect overflow for unsigned operations. I…
user9623401
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How do xIE, xPIE, and xPP work in handling traps and interrupts in RISC-V privileged?

I am new in RISC-V architecture. At present, I'm reading about RISC-V privileged in Volume II: Privileged Architecture. However, I have some concerns about the way xIE, xPIE, xPP bits work in handling traps and interrupts. Here is what the…
xuan tuan
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LDR and EQU in ARM Assembly

This my assembly code. a EQU 0x20000000 b EQU 0x20000004 c EQU 0x20000008 LDR R4, =a LDR R0, [R4] LDR R4, =b LDR R1, [R4] LDR R4, =c I had two questions. what after LDR R0, [R4] what goes inside R[4]? 0x20000000 or contents of the memory at…
m0ss
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What are the memory-related ISA features?

I'm preparing for a Computer Architecture exam, and I can't seem to answer this question: The following code is useful in checking a memory-related ISA feature. What can you determine using this function? #define X 0 #define Y 1 int…
juimdpp
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Why is my MARIE program addition becoming letters instead of numbers?

I am new to assembly and I'm not sure why my code isn't working. I'm inputing and displaying in ASCII format, I can see the 1 and 3, but why isn't the addition sum showing? My program is simply suppose to perform an addition. And display something…
Hello World
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