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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Are there bit (un)packing instructions in common x86_64 processor line mmx command for bytes?

dead hachers! Background: Maybe you know mmx packing/unpacking instruction set, what howewer works on bytes and larger volumes, like shorts, words, etc. Quesion: Are there any instructions for any x86_64 processor, to do the similar…
Peter Tschischik
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ARM Link register - non-leaf subroutine

I am wondering about, where the Link register is used in ARM CPU. As I understand it is storing return address of functions. But does every return address go to this register after function call or it is only related to leaf subroutine…
Bratw
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Do instruction set and instruction count mean the same when calculating cpu execution time?

I know cpu execution time = CPI * instruction count * 1/clock rate. in a certain problem, when three processors have the same instruction set, find the processor with the highest performance based on the CPI and clock rate values. So, I think that…
user9178840
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How to determine which processor has the highest performance

The following conditions exist. Consider three diff erent processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has…
user9178840
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How do I get the results of a fetch cycle in java based on an operating system? I am newbie to java I am looking for some advice

How do i get the fetch cycle working if i have to get the instruction address from memory and assign it to some area of ram? I am just starting to learn the language java any suggestions? I want to get the address from the instruction and add the…
Noel Powell
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What's the difference between the 2 groups of instructions given below regarding the non-use of the prefixes 66/F2/F3?

Section 3.1.1.1 on Chapter 3 of Volume 2 of Intel's documents says the following regarding NP: NP — Indicates the use of 66/F2/F3 prefixes (beyond those already part of the instructions opcode) are not allowed with the instruction. Such use will…
Belloc
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how +/- 4GB range is calculated for ADRP

I do understand, both ADR and ADRP is for PC relative addressing where with 20 bit of immediate address (for ADR) , it can point upto +/-1 MB (2^20) of address range but how +/- 4GB is calculated for ADRP. Apart from that I have simple snippet: int…
Milan
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BLSI instruction - Isolate lowest set bit

Bit Manipulation Set contains BLSI - this instruction Extracts the lowest set bit from the source operand and set the corresponding bit in the destination register Could you show an example illustrating what is referred to by the lowest set bit…
kiriloff
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Detect ARM instruction-set version?

I am writing a piece of code which depending on the different versions of instruction set implemented by various vendor might behave differently. These are the different versions of ARMv8 instruction set, like ARM v8.1, v8.2, v8.6. Is there any…
TheExcitedEngineer
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Can unsigned multiplication be performed using a signed multiplier?

For example the RISC-V ISA define four different multiplication instructions: MUL: signed x signed MULH: signed x signed MULHU: unsigned x unsigned MULHSU: signed x unsigned My question is: is it possible to reuse a single signed multiplier to…
Gabbed
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which data are loaded and not into register before execution?

Before a certain operation is to be performed on the data by ALU, Will the operands have to be loaded into the register from memory to perform? If yes, then why address field in the instruction may refer to the memory address of the operand?
Vembu karthick
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What is the value x12 at the end of the execution of this instruction in RISC-V? (WITHOUT RARS)

I need to know what is the value of x12 knowing that x13=10 ( without using rars ) these are the code lines loop: blt x13,x0,EXIT addi x13,x13, -1 addi x12,x12,2 jal x0, loop exit:
exiturnor
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"intel xeon silver 4216" whether the instruction set of this CPU supports SHA256?

It seems that AMD supports SHA256 and Intel does not. I checked that there is no relevant information. I ask questions here just hoping to get a positive reply
老男孩
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Why doesn't MOVZX work when operands have the same size?

With Z2 dword ?, mov eax, Z2 works fine but movzx eax, Z2 gives "invalid instruction operands" error. I am a little confused here: even though Z2 is of same size as eax, why couldn't assembly just accept movzx for this? It seems that movzx…
shivam
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Why Vacant locations in the address space are never accessible in RISC-V ISA?

I am reading The RISC-V Instruction Set Manual Volume I: Unprivileged ISA and i encountered a very strange statement to me. In subsection 1.4 Memory at the end of fifth paragraph is stated "Vacant locations in the address space are never…
ahmad sedigh
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