I hope you can help me on my RISC-V issue.
I am currently experimenting with the toolchain support for RISC-V's vector (RVV) instructions. From what I found on the internet, the spec is currently frozen at v1.0. GCC has a support RVV, but it is not actively maintained anymore. LLVM on the other hand has support for RVV.
So I went ahead and set up a Docker container with: RISC-V tools (Repo at basic-rvv), spike (latest commit) and LLVM (latest commit).
Next, I compiled a sgemm example with the following command: clang -march=rv32gcv --target=riscv32 --sysroot=/usr/local/riscv32-unknown-elf --gcc-toolchain=/usr/local -O2 sgemm.c -o sgemm.elf
. The command runs successfully and I get an elf file, which looks fine using objdump: it uses the vector instructions.
Now to my issue: Afterwards, I want to verify the binary with the instruction set simulator spike. Therefore, I ran: spike /usr/local/riscv32-unknown-elf/bin/pk sgemm.elf
, which ends up in an execution of an illegal instruction (see below for the full error message). The following OP fails: 0xb2905457
. I decoded the instruction with echo "DASM(0xb2905457)" | spike-dasm
--> vfmacc.vf v8, v9, ft0
, which looks fine to me.
I already went through the code of spike, and why it might fail, but I got lost.
Maybe you have an idea what's going wrong here? I have the feeling that my vector unit is misconfigured (setvl
instructions). I hope you guys can give me some support on this!
Thanks very much in advance! Tim
Error message from spike:
bbl loader
z 00000000 ra 000103cc sp 7ffffd70 gp 00020810
tp 00000000 t0 00000020 t1 bf06fb33 t2 00000000
s0 00020090 s1 00020b54 a0 00000004 a1 00020000
a2 00020010 a3 00000004 a4 00020b94 a5 0000001c
a6 bfed957a a7 00020b94 s2 00000000 s3 00000000
s4 00000000 s5 00000000 s6 00000000 s7 00000000
s8 00000000 s9 00000000 sA 00000000 sB 00000000
t3 3ea13dab t4 bf4b3713 t5 3ea6844f t6 3fdfe3d3
pc 000103ea va/inst b2905457 sr 80006620
An illegal instruction was executed!