1

I would like to do some byte manipulation using MIPS instruction set.

  • I have register $S0 which has 0x8C2E5F1E and register $S1 which has 0x10AC32BB.
  • I would like to store the second byte of $S0, 5F, into the third byte of $S1, AC.

My logic would be to store the byte of register $S0 into another register, shift it to the desired byte. Then I would and register $S1 with 0xFF00FFFF. Finally, I would just or the two registers. How does that sound? Is it correct? Any better way?

Any suggestions or solution would be appreciated.

Salchem
  • 118
  • 1
  • 2
  • 11

2 Answers2

1

Consider the following:

ori $t0 $s0 0xFF00 #extract byte 2
sll $t0 $t0 8 #shift to third byte

#create mask to clear third byte
lui  $t1 0xFF 
not  $t1 $t1

and  $s1 $s1 $t1 #clear third byte
or   $s1 $s1 $t0 #set third byte
Konrad Lindenbach
  • 4,911
  • 1
  • 26
  • 28
  • I know that. I am asking if that is the right logic to use for byte manipulation or there is a much shorter way, such move byte or something. – Salchem Nov 15 '13 at 15:59
1

For Release 2 and later, MIPS includes an Insert Bit Field instruction which takes bits starting at the least significant from one register and placing them into the specified range in a second register. Thus your byte insertion could be performed by the following:

// rotating right one byte rather than shift to preserve data
// without using an additional register
ROTR $S0, $S0, 8;
// insert LSbits from $S0 into $S1 starting at bit 16
// with size of 8 bits
INS $S1, $S0, 16, 8;
  • Great, exact answer I was looking for because I didn't know such instruction exist. However, your instruction has four operands?! so which format is it considered? does release 2 add a new format as well? Also Paul, if you may know, what's briefly difference between all releases, I know now they up to release 5 I think. – Salchem Nov 15 '13 at 16:26
  • @user2994448 The format has the standard 6-bit major opcode,then the source register [rs], then the destination register [rt](which is also a source), then two 5-bit immediate fields, then a 6-bit minor opcode; so it is similar to the format of SRA with tertiary opcode [bits 25:21] replaced with rs and the rd field replaced by a 5-bit immediate or to the format of SRAV with the tertiary opcode [bits 10:6] replaced with a 5-bit immediate and the rd field replaced by an immediate. –  Nov 15 '13 at 16:43
  • @user2994448 With respect to the different releases/versions of the MIPS ISA, that might be a decent question by itself (not sure if StackOverflow would be a good place for such a question). R5 adds hardware page table walking and distinguishes modules (licensed with base arch.--MultiThreading and DSP ASEs became modules, SIMD and Virt. were added) from Application Specific Extensions. No R4, R3 included microMIPS variable length encoding. I *think* the microcontroller ASE came in R3, but Rev. 1.01 of the manual is dated March 21, 2011. Before R2 there was MIPS I, II, III, and IV (IV==R2??). –  Nov 15 '13 at 17:03