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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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In the risc-v architecture, what do the bits returned by the mulh[[s]u] operation look like?

TLDR: given 64 bit registers rs1(signed) = 0xffff'ffff'ffff'fff6 and rs2(unsigned) = 0x10 does the riscv mulhsu instruction return 0x0000'0000'0000'000f or 0xffff'ffff'ffff'ffff or something else entirely to rd? I am working on implementing a…
BBSLIMS
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Breakdown of different instructions in executables

Other than the more common instructions like mov, add, call, ...etc I was curious about which instructions are most commonly used out of the 1500 or so instructions (it seems like 15 million). I wrote the following one-liner to check the counts of…
David542
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What sort of tools should I use in C++ to create a simple RISC-V disassembler?

I am looking to create a simple RISC-V disassembler in C++. The goal is to be able to take a .bin file, composed of separate bytes in hexadecimal, and parse those bytes into readable, formatted RISC-V instructions. I suppose it could be done using…
EthanR
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How to determine misprediction penalty?(CPU pipeline)

I was reading a textbook which says: Assume the probability of misprediction is p, the time to execute the code without misprediction is TOK and the misprediction penalty is TMP. Then the average time to execute the code as a function of p…
user9623401
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why use 32-bit register when the data type is 64-bit?

I was reading a textbook that has an exercise that generates assembly code based on C code: C code: long arith(long x, long y, long z) { long t1 = x ^ y; long t2 = z * 48; long t3 = t1 & 0x0F0F0F0F; long t4 = t2 - t3; return…
user9623401
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can we move content from smaller register to larger register

For example, can we do: movl %eax,%rdx // l means 32 bits while rdx is 64 biregister so if we move 32 bits content of %eax to %rdx, then only the low order 32 bits of %rdx get updated?
user11224591
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is x86-64 is just an alias name of EM64T?

I was reading a book which describe a historical perspective: Pentium 4E (2004, 125 M transistors). Added hyperthreading, a method to run two programs simultaneously on a single processor, as well as EM64T, Intel’s implementation of a 64-bit…
user11224591
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AMD Open64: Optimized math functions

Does Open64 has something equivalent to Intel Short Vector Math Library Operations. Thank you.
pic11
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RISC-V PMP Address Configuration

I am currently learning about PMP in RISC-V, I understand about the TOR, but I'm getting difficulties to understand NA4 and NAPOT configuration Can someone make an explanation ? My assumption is, if my pmpaddr is 0xFFFFFFFE then it means my pmp…
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Does x64 support imply BMI1 support?

It it safe to assume that x64 builds can use TZCNT without checking its support through cpu flags?
Pavel P
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Where to view the program counter (PC) and instruction register (IR) in gdb

Is it possible to view the current program counter and instruction register in gdb? Here is the output of a basic C program (add an int and return it) in gdb on ubuntu14: I thought I'd see something like pc or ir but perhaps it's either stored as…
David542
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How do VLIW processors deal with variable-time operations?

The concept of a very long instruction word CPU architecture is straightforward enough; as summarized on https://en.wikipedia.org/wiki/Very_long_instruction_word one VLIW instruction encodes multiple operations, at least one operation for each…
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Is it possible to combine CPUID and Instruction set emulation arguments in Intel SDE

Running sde.exe -nhm -bmi1 1 -- TestConsole.exe command don't take into account the -bmi1 1 option. It emulates nhm instruction set correctly but doesn't emulate the bmi1 instruction set. Is it possible to combine them some other way?
ptp
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x86 dissasembler that shows instruction extensions needed

I need to check the minimal set of x86 instruction extensions needed to execute a given binary object (not a general binary, but the output of gcc -c somefile.s). Doing it by hand is time consuming and error prone. I am looking for an automated…
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Why is it that the smaller instruction set of RISC architecture's does not necessarily contribute to a lower CPU time when compared to CISC?

Recently had this T/F question on a Comp. Systems quiz: Consider the CPU time formula: CPU Time = IC × CPI × (clock cycle time). If we only compare the first term IC, RISC performs better. And the answer was false. Can someone explain why this is?…
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