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I am designing a cell SPE processor. I have to check for data hazards before I take data from register file. What is the best way to identify the number of stall cycles necessary and what design decisions should I take about where to stall the pipeline? I am looking for a general view on the subject.

jlf
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Brahadeesh
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  • do you design a verilog of newer version of SPE or do you just programming an existing SPE? – osgx Apr 08 '11 at 14:25
  • designing a newer version of SPE. Lesser instructions but taken from all types. But same pipeline. – Brahadeesh Apr 08 '11 at 14:27
  • try to look here http://books.google.com/books?id=TkBC2q90NM8C and here http://books.google.com/books?id=-1kX4CV-IdQC&pg=PA909 and http://books.google.com/books?id=JEYKyfZ3yF0C&pg=PA22&dq=stall+pipeline+cpu – osgx Jul 07 '11 at 00:30
  • Thank you. I have finished the project. But I'll take a look anyway. – Brahadeesh Jul 13 '11 at 15:28

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