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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Kernel mode for user program

I am aware that Kernel mode is a privileged such that in kernel mode all hardware capabilities and all instructions in instruction set are available. I am also aware that when we make a procedure call (say read()) it in turn makes a system call. But…
Rahul Patel
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PDP 8 instruction set length comparison

Comparing difference between 8080 and PDP-8. 8080 supports instructions of variable length, but does PDP-8? Does PDP-8 support instructions of variable length?
Rachel
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How to solve dyld: Library not loaded on MacOS?

I will do some experiments with X86 ISA by using PIN Binary Instrumentation Tool. I downloaded the tool from https://software.intel.com/en-us/articles/pin-a-binary-instrumentation-tool-downloads . You can see the ./pin file. However, when I try to…
Mahsun ALTIN
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Looking for Mapping between RISC-V base 32I Instructions and their Opcodes

Is the encoding of risc-v instructions to opcode bits standardized? If so, where can I find the encoding table at least for the base 32I instructions?
Josina
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Sum of Absolute Differences in Assembler

Lets assume the function in pseudocode. int abs_diff(int l, int r) { int abs_diff = abs(l - r); return abs_diff; } I was able to implement this function in assembler. abs_diff: sub $t1, $a0, $a1 sra $t2,$t1,31 xor…
waqarrt
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Registers in the CPU of a computer

I just want to verify if the CPU itself supports names of "registers". I mean arg0 arg1 arg2... etc is at the end "names". Does the CPU support also names?! I'm not asking about the register itself, I'm asking whether the CPU supports names of the…
Ryan
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What is the AMD ryzen 7 2700 instruction set (for creating an assembler)

I want to create my first assembler so I can program my own program languages, my own OS and so on. There's just one problem: I can't find an instruction set for the ryzen 7 2700. I already found out that it uses the zen+ architecture but I couldn't…
Dzenan
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amd and intel programmer's model compatibility

I have read through Intel's Software Development Guide's (vol 1-3). Without doing a doing a similar read through AMD's Programming Guides (vol 1-5), I am wondering what aspects of Intel and AMD's programming model are the same. Of course, even…
Abel
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Why sw instruction in mips using byte as offset unit?

I have a question about the offset units used in MIPS32 instructions. I just noticed that memory access instructions like lw $t0, offset($s1) has offset of unit byte, while branching instructions like beq $r1, $r2, L1 and jump j SOMEWHERE both have…
Kindred
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Why the RISC instruction sets usually do not contain register to register copy instruction?

I had this question on my exam and i am confused because as far as i know that move $t0, $a0 # COPY $A0 TO $T0 in MIPS instruction provides that and MIPS is a RISC processor. Am I missing something?
roffensive
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aesimc instruction gives incorrect result

I'm trying to implement AES cryptography using the AES machine instructions (basing it on Intel's white paper) available on my Sandy Bridge. Unfortunately, I've come to a halt in the phase of generating the round keys for decryption. Specifically,…
Morten Kristensen
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What is the point of on-chip hardware accelerators, instead of that functionality being added as an instruction to the ISA?

I get that if a specialized operation is known to be common, it makes sense to do it in hardware. But at that point, why not make it a part of the ISA so it can be even faster? Is there a benefit to making it a co-processor that communicates…
KenArrari
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How to check what cpu features can be used in my current system image?

I found on the internet a performance tip for Julia: compile the system image for your architecture. Besides the fact, that the process gives an error julia> include(joinpath(Sys.BINDIR, Base.DATAROOTDIR, "julia", "build_sysimg.jl")) julia>…
Adam Ryczkowski
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How loops are implemented in PIC24F assembly code

Below is the disassembly of following C code: 268: while (Counter < 250) 269: { 270: Counter++; 271: } Disassembly: 268: while (Counter < 250) 001B08 …
M Sharath Hegde
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Does a memory barrier acts both as a marker and as an instruction?

I have read different things about how a memory barrier works. For example, the user Johan's answer in this question says that a memory barrier is an instruction that the CPU executes. While the user Peter Cordes's comment in this question says the…
Steve
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