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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Why are name dependencies (WaR, WaW) in ILP architectures problematic?

Assume the following two instructions are executed simultaneously: addi $t0, $t1, 4 addi $t1, $t2, 4 It's an anti-dependence, or Write-after-Read. Assuming they are executed at the same time, wouldn't the first instruction still read the correct…
smatts
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Assembly x86 error with SHL eax, ecx

Im having trouble with this compile error in my code for an Assembly x86 class, A2070: invalid instruction operands the line is shl eax, ecx ecx should be looping (decreasing by 1) and never be greater than 5 at this moment, so why can't I shift…
Collin Hurst
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32 bit PPC rlwinm instruction

I'm having a bit of trouble understanding the rlwinm PPC Assembly instruction (Rotate Left Word Immediate Then AND with Mask). I am trying to reverse this part of a function rlwinm r3, r3, 0, 28, 28 I already know what r3 is. r3 in this case is a 4…
thehaxdev
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Understanding STM8 pipelining

I’m trying to understand STM8 pipelining to be able to predict how much cycles my code will need. I have this example, where I toggle a GPIO pin for 4 cycles each. Iff loop is aligned at 4byte-boundary + 3, the pin stays active for 5 cycles (i.e.…
rumpel
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Minimum machine instructions for C

I've built an 8 bit computer out of some ( I mean a tonne ) of wires and 74xx series TTL gates. The computer was slow and it was tedious to program things. I made a small interpreter? I guess that's the correct term for my version of assembly…
E Skal
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MSP430 SWAP bytes explanation assembly

When we have a code like this : main: MOV #SFE(CSTACK), SP ; set up stack ;;; some instructions ....... ; load the starting address of the array1 into the register R4 MOV.W #arr1, R4 ; load the starting…
user629034
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Why are systemcalls used in assembly programming?

In my quest to understand what happens in the lowest level in a computer, I recently found out something so that I can start coding in assembly: https://0xax.github.io/asm_1/ section .data msg db "hello, world!" section .text global…
d4rkl0rd
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How to use Intel's RDRAND using inline assembly with .Net

I'm using an Intel Ivy Bridge CPU and want to use the RDRAND opcode (https://software.intel.com/en-us/articles/intel-digital-random-number-generator-drng-software-implementation-guide) in C#. How can I call this CPU instruction via C#? I've seen an…
Mike de Klerk
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In MIPS, why can a jump instruction set the program counter to a 28-bit target address

In MIPS, a 32-bit jump instruction consists of 6-bits for the opcode and 26-bits for the target (destination) address that we want to set the program counter to. However, it is possible to set the program counter to a 28-bit target address. How is…
jshapy8
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What is the difference between bytecode and microcode?

I was reading on wikipedia about machine code, microcode and bytecode. It seems that microcodes are something more low-level than machine code, while bytecodes seem to be more high-level. I didn't realy get how something can be more low-level than…
Gabriele Scarlatti
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Guaranteed-invalid ARM/Thumb2 M3 instruction

I would like to write a magic value into program memory on an ARM M3 embedded device. I can just define an arbitrary constant (other than 0xFFFFFFFF, which is blank flash!) and program that at some fixed address with the help of linker sections.…
Inductiveload
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Differentiate data from instructions in ARM

In (32-bit) ARM Linux kernels, how to differentiate data embedded in the code section, from instructions? It is better to have a light-weight approach, like bit masks, which can be easily implemented. It is not wise to embed a dissembler into the…
WindChaser
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How instruction set randomization works, roughly

I read about instruction set randomization in modern processors where a processor randomizes the instruction sets to avoid code injection attacks. Actually, Wikipedia explanation is not clear to me. Kindly, can someone explain the process of it in a…
Kristofer
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Merge bit sequences a and b according to a mask

According to the bit twiddling hacks website, the operation unsigned int a; // value to merge in non-masked bits unsigned int b; // value to merge in masked bits unsigned int mask; // 1 where bits from b should be selected; 0 where from…
Vincent
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How to write loop in C so compiler may use branch on zero after decrement

Processors are known to have special instructions for decrementing a counter and branch if the counter is zero with very low latency as the branch instruction does not need to wait for the counter decrement passing through an integer unit. Here is a…
Andreas
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