Stack Overflow
Stack Overflow

Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

736 questions
2
votes
1 answer

is fcvtzs d0,d0 really an AArch64 SIMD instruction?

gcc seems to classify fcvtzs d0,d0 as as SIMD instruction, but clang does not. Who is right? $ cat toto.s fcvtzs d0,d0 $ aarch64-linux-gnu-gcc-10 -mcpu=cortex-a53+nosimd -c toto.s toto.s: Assembler messages: toto.s:1: Error: selected processor…
David Monniaux
  • 1,948
  • 12
  • 23
2
votes
1 answer

Scan binary for CPU feature usage

I am debugging an application that runs properly on an Intel CPU, but not on another, newer AMD processor. I suspect that it may have been compiled to use certain Intel-specific instructions, which leads to the crashes. However, I am looking for a…
MrDrMcCoy
  • 351
  • 4
  • 18
2
votes
1 answer

Why do x86 mul and div instructions only take a source operand?

In x86 assembly, most instructions have the following syntax: operation dest, source For example, add looks like add rax, 10 ; adds 10 to the rax register But mnemonics like mul and div only have a single operand - source - with the destination…
Michael Moreno
  • 947
  • 1
  • 7
  • 24
2
votes
0 answers

Program behavior when a jump is out-of-range

I'm wondering what would be the program behavior if a jump is out of range. What factors affect the program behavior (compiler, processor, ISA, or factors I don't know). Also how may I find it out (in ISA manual?) for a specific hardware?
minglotus
  • 83
  • 6
2
votes
1 answer

Are SIMD and VLIW instructions the same thing?

What exactly is the difference between SIMD (Single Instruction Multiple Data) and VLIW (Very Long Instruction Word)? Is one a subset of the other? Or are they two completely difference things?
Izzo
  • 4,461
  • 13
  • 45
  • 82
2
votes
1 answer

Finding maximum number of register counts from instruction size, op-code size, and number of operands

I've been trying to wrap my head around how to achieve the answer. I'd like to say I did my own research but either I'm not searching the right questions or I'm blind. Can someone please explain the logic behind finding the answer? I am at a…
Mark Kobain
  • 23
  • 2
2
votes
1 answer

Problems using risc-v timer interrupts and simulating with spike

I'm trying to make a timer interrupt, I have the following risc-v_tools installed riscv64-unknown-elf-gcc toolchain, spike simulate and pk . this is my code: #define MTIME *((volatile uint64_t *) 0x02000000 + 0xbff8) #define MTIMECMP …
Juan Romero
  • 81
  • 6
2
votes
2 answers

Is every cpu instruction implemented by logic gates at its core?

Is every operation done by the CPU implemented by simple logic gates such as AND, OR, XOR gates? For example a half adder is implemented with an AND + XOR gate. What about: The rest of the Arithmetic Logic Unit (subtraction, multiplication,…
Dan
  • 2,694
  • 1
  • 6
  • 19
2
votes
1 answer

Is there any official document for proving that JL and JNGE work in the same way?

I have to prove that JL and JNGE are the same and specifically both mean " if (left op < right op) then jump " I can see some features from University lecture resources and stackoverflow giving thoughts about the…
sy choi
  • 43
  • 1
  • 6
2
votes
1 answer

x86_64 Instruction pipelining: Instruction execution order

I have some doubts on Instruction pipelining. I have an assembly 0x111: div %ecx 0x112: add $0x13,%ecx #The address 112 is not real, I just kept to show that there is no instructions between div and add The program counter,RIP points to…
Franc
  • 319
  • 9
  • 28
2
votes
2 answers

Do instruction sets like x86 get updated? If so, how is backwards compatibility guaranteed?

How would an older processor know how to decode new instructions it doesn't know about?
user6529117
2
votes
1 answer

Pseudoinstuctions and software abstractions in Assembly

This is more of a general theoretical question. I am learning some assembly languages and have noticed that some software, such as MARS for MIPS, implements abstractions that don't exist in the architecture's real instruction set which seem to be…
Lara
  • 89
  • 7
2
votes
2 answers

What exactly is a machine instruction?

The user's program in main memory consists of machine instructions and data. In contrast, the control memory holds a fixed microprogram that cannot be altered by the occasional user. The microprogram consists of microinstructions that specify…
james
  • 53
  • 5
2
votes
2 answers

Is it legal to have same register as operands in one instruction?

For example, below is a X86-64 instruction: movq (%rdi),%rdi It reads the content (pointed by %rdi) and set this content to %rdi, which is valid in sequential logic? Or do we have to assign it to a different register and move it back as: movq…
user11224591
2
votes
1 answer

Why decrement %rsp when everything can be done via registers?

Below is my code: C code // this function might look weird, just for demo purpose void func4(int x, int y, int z) { int t = z - y; int k = t >> 31; t = (t + k) >> 1; k = t + y; if(k <= x) { t = 0; if(k >= 1) { …
user11224591
1 2 3
…
49 50