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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Do BGEZAL and BTLZAL modify $31 if branch not taken?

According to this specification of MIPS BGEZAL does the following operation: I: tgt_offset ← sign_extend(offset || 02) condition ← GPR[rs] ≥ 0GPRLEN GPR[31] ← PC + 8 I+1: if condition then PC ← PC + tgt_offset endif From what I understand from…
gorilon
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How do IBMs lis and ori instructions work?

I want to know how do lis and ori instructions work? There is a description IBM description which i cannot understand well. Could someone explain to me what is the result on this example: lis r1, 0x0028 ori r1, r1, 0x776F
AR93
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RISC under CISC ISA

I am learning about CPU architecture and it is bit confusing. Is it correct that old microprogrammed CISC CPUs would translate ISA instruction into series of simple (1 cycle) microinstructions?(and that by RISC philosophy ISA instruction basically…
Mr. Vader
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emu8086 mistake:unknown opcode skipped: 65 not 8086 instruction

org 200h data segment ;upper_case sA db 'Alpha', 20h, '$' sB db 'Bravo', 20h, '$' sC db 'Charlie', 20h, '$' sD db 'Delta', 20h, '$' sE db 'Echo', 20h, '$' sF db 'Foxtrot', 20h, '$' G db 'Golf', 20h, '$' H …
Zhao
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Why does INST_PTR (instruction pointer) values of the same program change for different runs?

In Intel's PinTool, you can print out the "instruction address" of every instruction in a program by using either IARG_INST_PTR or INS_Address. I've observed that running the same program at different point in time produces different instruction…
kc2uno
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Does Java use AES-NI when available?

I just heard of the instruction set extension AES-NI. Does Java's JIT compiler compile the application to use AES-NI if it is available to enhance performance? And if yes, does it also do so if it is not sure that AES will be used (like when using…
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Which factors affect the needed compiler?

I'm learning C and I don't understand what factors determinate the needed compiler and why. Let's say I'm having C code that is a little console application and I want to compile it for a specific platform. This platform would have a specific OS and…
MinecraftShamrock
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Equivalents to Z80 DJNZ instruction on other architectures?

First a little background. The z80 CPU has an instruction called DJNZ which can be used in a similar manner as a for loop. Basically DJNZ decrements the B register and jumps to a label if not zero. For example: ld b,96 ;…
Justin Ethier
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is bytecode treated as instruction set for JVM?

I was reading about instruction set in wiki and I came across this paragraph: Some virtual machines that support bytecode as their ISA such as Smalltalk, the Java virtual machine, and Microsoft's Common Language Runtime, implement this by…
brain storm
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Gcc compilation for different targets

I was just trying to understand something about cross compilers which made me ask this question. gcc is a cross-compiler. By default what it the target architecture for gcc compilation if none is specified is the native target on which I am…
user3144089
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Are modern GPUs considered to be RISC based or CISC based?

I'm trying to figure out if modern GPUs have a reduced instruction set, or a complex instruction set. Wikipedia says that it's not the size of the instruction set, rather how many cycles it takes to complete an instruction. In RISC processors, each…
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x86 asm instruction set: Any _searchable_ offline reference?

I'm somewhat new to assembly and have to look up the x86 instructions every now and then. Searching the web for every other opcode gets annoying after a while. Then there are the Intel Reference Manuals, but the contents page doesn't have direct…
int3
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Did the Streaming SIMD Extensions replace x87 instruction set?

I know that the SSEs are an alternative to the x87 floating point instruction, but is the x87 FPU still implemented in modern CPUs like Ivy-Bridge or Haswell? Did SSEs replace the x87 instruction set?
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how to simulate 5 stage of pipe line in c++?

I am trying to simulate 5 stage of pipeline. I have saved all the instruction into a struct. ( basically done with the stage of lixcal analysis ) eg: ADD R1 R2 R3 // R1 = R2+ R3 ... struct pipe{ int pc, string instruction , int r1, int r2....} now…
pokche
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gcc options to use i87, AVX simultaneously but nor SSE

When compiled for processor that support AVX extension (say -m64 -march=corei7-avx -mtune=corei7-avx is applicable), does it make sense to use -mfpmath=both -mavx keys at the same time? Does not it so much that it causes the compiler to use three…
Tomilov Anatoliy
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