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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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Optimal way of emitting multiple asm instructions from single LLVM IR instruction

I am implementing an LLVM back-end for an accumulator-based processor. Currently, I seem stuck in the decision of how to match IR instructions correctly to the ISA. An example could be an LLVM IR instruction: %c = add %a %b Which would need to be…
Morten B.
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what is cfi_adjust_cfa_offset and cfi_rel_offset?

I am currently trying to understand the inner code of the glibc's syscall function. Below is the code (taken from here). /* In the EABI syscall interface, we don't need a special syscall to implement syscall(). It won't work reliably with 64-bit…
hongjo lim
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What is the difference between "jmp function" and "mov function, %eip"

What is the difference between jmp function and mov function, %eip Actually, What happens when i change the eip value forcefully? I know that a eip is instruction pointer that pointing the instruction that will be executed by CPU. This means that…
Joontaek Oh
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Why cant an immediate value be used in mul instruction?

I am writing instructions for the ARMv7 processor. I would like to know why I am not allowed to have a constant value in the MUL instruction itself? You're allowed with the ADD and SUB instruction so why not MUL? Cheers
Sam Rolls
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32-bit fixed instruction length in 64-bit memory space

I am currently reading up on the AArch64 architecture by ARM. They are using a RISC-like instruction set with a fixed instruction length of 32-bit while operating on 64-bit addresses. I am still new to the topic of ISA so my question is: how can you…
SuperTasche
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If a computer can be Turing complete with one instruction what is the purpose of having many instructions?

I understand the concept of a computer being Turing complete ( having a MOV or command or a SUBNEG command and being able to therefore "synthesize" other instructions such as ). If that is true what is the purpose of having 100s of instructions like…
E Skal
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Why is Page Size specified as part of Instruction Set Architecture?

I am trying to understand why is Page Size specified as part of an ISA. More specifically, I am looking for details where any of the hardware modules (MMU, TLB) (apart from the Operating System) use the Page Size information to provide a certain…
Uchia Itachi
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CMP and carry flag

Processor: MSP430 16 bit RISC Can someone explain the CMP instruction in terms of when the carry flag is actually set below. From the manual it says, CMP(.B) src,dst ..... dst - src If src is not equal to dst, will the carry flag be set? cmp r15,…
user7532311
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What is the K3D x86 ISA extension?

The Microsoft MASM language includes a .K3D directive. The docs are sparse: Enables assembly of K3D instructions. Inferring from other directives this seems to be an x86 ISA extension. I find no instance of the term in the entire Intel…
user6798019
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Instruction execution latencies for A53

I'm working on optimizing a function which uses floating point instructions. For bench marking I need to know execution latency of the instructions to know theoretical possible performance. I have found such manual for A57:…
Vikram Dattu
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Detecting SIMD instruction sets to be used with C++ Macros in Visual Studio 2015

So, here is what I am trying to accomplish. In my C++ project that has to be compiled with Microsoft Visual Studio 2015 or above, I need to have some code have different versions depending on the newest SIMD instrunction set available in the CPU of…
user123443563
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Wrapping my head around hardware representations of numbers: a hypothetical two's complement question

This is a super naive question (I know), but I think that it will make for a good jumping off point into considering how the basic instruction set of a CPU actually gets carried out: In a two's complement system, you cannot invert the sign of the…
tel
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How can one validate output of x86 commands?

I have a difficulty in figuring out the appropriate addresses and values stored in particular registers when x86 commands are executed. I try to execute the following instructions with the initial values assigned to these two registers: eax =…
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How can I utilize the 'red' and 'atom' PTX instructions in CUDA C++ code?

The CUDA PTX Guide describes the instructions 'atom' and 'red', which perform atomic and non-atomic reductions. This is news to me (at least with respect to non-atomic reductions)... I remember learning how to do reductions with SHFL a while back.…
einpoklum
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Is CPU only compatible to one kind of instruction set architecture?

I start to explore in the area of computer architecture. There are 2 questions about ISA that confuse me. As far as I know, there are different kinds of ISA such as ARM, MIPS, 80x86, etc. I wonder whether a CPU can only specifically read one kind…
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