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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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How does the OS interact with peripherals like sound cards/ video cards etc

As far as I understand it, any program gets compiled to a series of assembly instructions for the architecture it is running on. What I fail to understand is how the operating system interacts with peripherals such as a video card. Isn't the driver…
Matt
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Intel 8080 instruction... what is the etymology of the "DAD" instruction mnemonic?

I am learning about the Intel 8080 processor in Charles Petzold's excellent book Code. The DAD instruction was explained as far as what it accomplishes, but I have a weird thing about alphabetical codes like this where I have to know what they…
The111
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Repeat prefixes and mandatory prefixes in x86

In my quest of writing a small disassembler for linux specific to x86 arch, I'm faced with a small issue. It's with regard to mandatory prefixes and repeat prefixes. Looking at the Intel docs [1], it's said that repeat prefixes are 0xf2 or 0xf3, and…
Hrishikesh Murali
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How are the bytecodes for MIPS nop and sll differentiated?

As far as I'm aware both instructions have opcode and function code of 0, so how does the computer know which one it's doing?
George Bland
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Do all CPUs of the same architecture run the same Assembly instructions?

Recently, I saw a video of someone writing ASM, they only mentioned that the code is for the x86_64 architecture, with no mention of the specific CPU. At university I was taught to look at the CPU's Instruction Set, OP Code, memory map, etc...…
HasanTheSyrian_
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Different encoding for arm64 "add x1, sp, x2, lsl #1" than with xzr

The add x1, sp, x2, lsl #1 instruction is supposed to be an "Add (shifted register)" but I have problems with the encoding to differentiate when SP and XZR is used. I'm astonished with the results. This is the encoding for the "ADD (shifted…
raff
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Need help in adding more functionality to MIPS Single Cycle Datapath

I am trying to add jal functionality to the following but I am stuck with how does it work. I know that it stores the old PC+4 value in the $ra register and then transfers the control to the function which transfers back the control by return $ra…
user379888
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Are there any problems for which SIMD outperforms Cray-style vectors?

CPUs intended to provide high-performance number crunching, end up with some kind of vector instruction set. There are basically two kinds: SIMD. This is conceptually straightforward, e.g. instead of just having a set of 64-bit registers and…
rwallace
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What exactly do the gcc compiler switches (-mavx -mavx2 -mavx512f) do?

I explicitly use the Intel SIMD extensions intrinsic in my C/C++ code. In order to compile the code I need to specify -mavx, or -mavx512, or something similar on the command line. I'm good with all that. However, from reading the gcc man page,…
JB_User
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Are x86 atomic instructions also atomic to DMA reads?

Assume that an x86(x64) CPU is executing atomic instructions (e.g., lock cmpxchg) in a certain memory region. At the same time some device is also performing DMA reads from the same memory region without letting the CPU know. Now do the atomic…
IcicleF
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What is the difference between N.E. and I in Intel manual?

In Intel's manual for Intel 64 and IA-32 instruction set section 3.1.1.5, it introduces 64/32-bit mode column in the instruction summary table. For 64-bit mode support, it says: I - Not supported N.E. - Indicates an instruction syntax is not…
Evian
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Does Python hashlib's sha256 employ the Intel SHA extensions?

Does CPython hashlib's SHA256 employ the Intel SHA extensions ? If yes, since which version(s)? Since CPython uses OpenSSL for its crypto primitives it should also use its hardware acceleration capabilities (AESNI-SHA256 was added to OpenSSL between…
Florian Sesser
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Why are there no NAND, NOR and XNOR instructions in X86?

They're one of the simplest "instructions" you could perform on a computer (they're the first ones I'd personally implement) Performing NOT(AND(x, y)) doubles execution time AND dependency chain length AND code size BMI1 introduced "andnot" which…
MrUnbelievable92
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CPUs with instructions with more than two branch destinations

Processors usually come with jmp-instructions to continue from a different fixed location and may depend on some condition. So the out-degree is two at most. Are there any processors out there that have a single instruction that branches to one of…
The Techel
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If LDT does not exist in 64-bit architecture how are 32-bit systems that use it emulated on a 64-bit architecture?

I read that LDT (Local Descriptor Table) does not exist in 64-bit architecture and was wondering how a 32-bit system that uses it is emulated.
Kamil Abdurahim
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