Questions tagged [ice40]
37 questions
1
vote
0 answers
ice40 UltraPlus Mobile Development Platform
I have a Lattice iCE40 UltraPlus Mobile Development Platform, new piece ordered from Digikey. This has 4 iCE40 UltraPlus devices (iCE40UP5K-UWG30)
I have compiled the icestorm suite, and ran the "rgb.v" example in "icestorm/examples/up5k_rgb" as…
santvasu
- 11
- 3
1
vote
1 answer
ICE40 up5k Internal internal oscilator and ip's
i can see that icestorm support ice40 ultra plus up5k fpga,
but this chip has internal osc, is there any example what i use it ? of course using yosys, icestorm (opensource)
and is there some examples where i can use build in IP,s such as SPI,…
Miroslav Talasek
- 11
- 1
1
vote
1 answer
Yosys optimizes away ring oscillator on ice40 FPGA
Im trying to implement a simple ring oscillator for an ice40 FPGA using yosys (0.7) as follows:
module ringosc(input clkin,
output out);
(* keep="true" *)
wire [100:0] ring;
assign ring[100:1] = ~ring[99:0];
…
farindk
- 260
- 3
- 15
0
votes
1 answer
Verilog Coding Not Performing as Expected
new using Verilog and coding the Upduino v3.1. Set a PLL module, using its output clock to increment a counter until it reaches 2000, and toggle the output LED. This is code:
module main_pll(REFERENCECLK, PLLOUTCORE, LED);
input REFERENCECLK; …
gus
- 355
- 2
- 5
- 19
0
votes
1 answer
Use PLL in Lattice Radiant
Using Radiant to program Upduino v3.1 (ICE40UP5K) to implement a PLL created using the IP wizard. Once created, this is the .vhd code where initialized the PLL as well:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity…
gus
- 355
- 2
- 5
- 19
0
votes
1 answer
Verilog ICE40 LED Driver as IO - SB_IO_OD, how to assign
New to verilog here.
The Ice40 has an RGB led driver that can also be assigned as a normal IO.
Trying to access the pin without setting it as IO will give this error one IceCube2
Error during constrained IO placement E2792:…
Damien
- 1,492
- 10
- 32
0
votes
2 answers
Cascading BRAM in iCE40 FPGA
I'm really new to FPGA and Verilog. I've been working on the Tri-SPI PHY controlling Noritake Itron VFD Display. One of the feature I want to implement is the framebuffer memory on the FPGA itself. I'm using the iCE40LP1K which has 64kbit BRAM…
TinLethax
- 11
- 3
0
votes
0 answers
USB Errno 5 when uploading to a TinyFPGA BX with tinyprog
I have a TinyFPGA BX board that is connected to a Mac (Big Sur) I am trying to upload a new bootloader to this board using tinyprog (https://pypi.org/project/tinyprog/). I am running this with
>>>from tinyprog import *
>>>from tinyprog.__main__…
0
votes
1 answer
iCE40 Ultra Plus 5k -- how to set PLL (without propietary GUI tools)
Is there any way to configure the iCE40 Ultra Plus 5k PLL without using the fancy propietary tools like Lattice Icecube2 / Radiant software.
Official PLL programming guide (source) only shows how to use mentioned propietary GUI tools (ch. 4)
71GA
- 1,132
- 6
- 36
- 69
0
votes
1 answer
Xilinx equivalent primitive of ICE40 SB_IO primitive?
I have an example project in Verilog originally was for ICE40 FPGA, I want to import it to Xilinx FPGA for resource reason. There is this SB_IO primitive in ICE40 that defines input/output ports. I don't quite understand it and wondering if there is…
TerryL
- 1
0
votes
1 answer
Understanding Organization of the CRAM bits in bitstream .bin file
For an iCE40 1k device, Following is the snippet from the output of the command "iceunpack -vv example.bin"
I could not understand why there are 332x144 bits?
My understanding is that [1], the CRAM BLOCK[0] starts at the logic tile (1,1), and it…
Sajjad
- 111
- 1
- 13
0
votes
1 answer
reading multiple block ram indexes in one write clock cycle
I have an application where I'm continuously writing to a block ram at a slow clock speed (clk_a) and within this slow clock cycle need to read three indexes from the block ram at a fast clock speed (clk_b) to use these values as operands in a math…
ke10g
- 27
- 4
0
votes
1 answer
ice40 clock delay, output timing analysis
I have an ice40 that drives the clock and data inputs of an ASIC.
The ice40 drives the ASIC's clock with the same clock that drives the ice40's internal logic. The problem is that the rising clock triggers the ice40's internal logic and changes the…
Dave
- 23
- 1
- 4
0
votes
1 answer
What are PIP alternative in arachne-pnr?
While going through the router.cc the file of arcahne-pnr, I am unable to understand, how are the programmable interconnect pins PIPs routed? Does it seem PLL is representing the PIPs in the code? Could somebody help to make me clear, what…
qah
- 27
- 8
0
votes
3 answers
Trouble getting YOSYS to infer block ram array (rather than using logic cells) verilog ice40
I've been having trouble the last little while with a project that uses look up table arrays quite a bit and getting yosys to infer them as block ram. Yosys keeps thinking one or the other of my arrays should be implemented using logic…
ke10g
- 27
- 4