Verilog Coding Not Performing as Expected

Question

new using Verilog and coding the Upduino v3.1. Set a PLL module, using its output clock to increment a counter until it reaches 2000, and toggle the output LED. This is code:

module main_pll(REFERENCECLK, PLLOUTCORE, LED);

input REFERENCECLK;  
output PLLOUTCORE;
output wire LED;

wire pllout;
reg [15:0] counter;
reg temp;

pllG pllmpd(.ref_clk_i(REFERENCECLK), .rst_n_i(), .outcore_o(PLLOUTCORE),.outglobal_o());

assign pllout = PLLOUTCORE;
assign LED = temp;
initial temp <= 1'b0;
initial counter <= 16`b0;

always @(posedge pllout) begin
    counter <= counter + 1;
    if (counter == 2000) begin
        counter <= 0;
        temp <= ~temp;
    end
end

endmodule

The output LED doesn't toggle and not clear what the issue could be.

Can you please help me understanding what I am doing wrong?

Thanks, Gus

1) simulate first and debug logical issues; 2) check if clock and pllout work. 3) check synthesizer errors and warnings; 4) initial blocks might not be synthesizable, use reset instead. — Serge, Jul 17 '23 at 19:36
how do you know it is not toggling? What are the frequencies used? — Christian B., Jul 17 '23 at 20:03
Serge - unfortunately, I don't have access to a verilog simulator. There are no errors related when synthetizing the code - the software used (Radiant from Lattice) properly generates the bin file to load in the board — gus, Jul 17 '23 at 20:19
Christian B. - the synthetized code is properly programmed into the FPGA, and output to be toggled is an LED (as the code mentioned), I can see the LED been bright the whole time, without changing over time, as I should expect by toggling — gus, Jul 17 '23 at 20:21
The radiant software is bundled with ModelSim. From personal experience I highly recommend to get used to simulation software for FPGA programming. — Christian B., Jul 17 '23 at 20:22
Assuming that something is not toggling by bare eye is a common mistake. E.g. Take the example I posted and reduce the counter size. You will notice that the toggling will "disappear" for increased frequency. See "Flicker fusion threshold" for details. — Christian B., Jul 17 '23 at 20:25
@OP https://edaplayground.com/ is a good place to start simulations. — Serge, Jul 17 '23 at 20:58

score 1 · Accepted Answer · answered Jul 17 '23 at 20:18

1

ice40 sets all registers to zero and IIRC unconnected port to GND (1'b0). Thus, the PLL will not start if nothing is passed to rst_n_i. The following code was tested on an ice40UP5K-B-EVN:

module main(    
    input   wire    REFERENCECLK,//12 MHz clock on pin 35 (GPLL_IN/PCLKT0_1)
    output  wire    PLLOUTCORE, // pin 28
    output  reg     LED // will blink with ~3 Hz, mapped to pin 40 (RGB1=green LED)
    );

reg [21:0] counter;// ice40 set everything to zero as default

always @(posedge PLLOUTCORE)
begin
    counter <= counter + 1;
    LED     <= counter ? LED : ~LED;
end
    
testpll pllmpd(
    .ref_clk_i(REFERENCECLK),
    .rst_n_i(1'b1), //this is important, else the nrst will be held at 0
    .outcore_o(PLLOUTCORE), // 24 MHz out
    .outglobal_o()
    );

endmodule

answered Jul 17 '23 at 20:18

Christian B.

816
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11

Thanks again Christian! It does work - now if I want to toggle the led slower, i changed the line ```LED <= counter ? LED : ~LED;``` by ``` if (counter == 2000) begin counter <= 0; temp <= ~temp; LED <= ~temp; end``` creating the variable temp in the beginning of the code as a 1 bit reg, but it does not work as expected. How would you change the toggle frequency? – gus Jul 17 '23 at 20:51
1

You can change the freq by changing the the counter size. Alternatively you can implement a kind of duty cycle sweep by reducing the counter to e.g. 7:0 and then change the condition to LED <= counter < XXX; - play a bit with the numbers. e.g. put XXX = 8'd10 or 8'd127 etc – Christian B. Jul 17 '23 at 20:54
Christian B - why ```LED <= counter ? LED : ~LED;``` works but setting the same as a if statement doesnt? ie setting like this: if (counter == 2000) begin counter <= 0; LED <= ~LED; end – gus Jul 18 '23 at 15:27
1

your condition would imply that the LED toggles states with 24/2000 MHz = 12 kHz. The condition in the example switches with 24 / 2^22 MHz = 6 Hz. 22 is the bit size of the counter. – Christian B. Jul 18 '23 at 18:32

Verilog Coding Not Performing as Expected

1 Answers1