Questions tagged [ice40]
37 questions
0
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1 answer
Yosys and Synplify compatible elements
I would like to write verilog that can be synthesized either using yosys (preferable) or the Lattice Radiant tool chain using Synplify (needed for encrypted IP from Lattice for example).
Most of the hard cells like the PLL have different names…
Venkat
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Loading of .hex file in SB_RAM2048x2 ROM and loading of .hex file in BRAM memory
I have no idea about SB_RAM2048x2 memory Usage for iCE40 Devices. I find iceimage.hex mecrisp-ice 0.8 , a memory initialization file ,is being loaded into ram.v .and ram.v is being used in other verilog file. I want to use the bram instead of this…
0
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having trouble setting up two GB_IO pins
I used the following code to set up my ICE40HX1K-VQ100 fpga to input
an external clock:
SB_GB_IO gb_io1 (
.PACKAGE_PIN( clk ),
.GLOBAL_BUFFER_OUTPUT( gclk )
);
This is for pin IOL_6B_GBIN7.
By itself, this works fine but I also needed to…
Steve Brown
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is it possible to change slew rate of pins with icestorm tools for the ice40 devices
I couldn't find any examples of pcf files setting slew or drive rates. I checked the tech paper that lists the io port primitives, and it seems possible to set the drive, but not the slew.
Matt Venn
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-1
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2 answers
programming iceStorm binary file to which address?
I'm trying the very first example supplied here: http://www.clifford.at/icestorm/
I'm trying to program the iCEblink40-HX1K board in windows using the digilent adept…
mime
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-2
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1 answer
JK-flip flop using gate level description in Verilog give me a timming error
I still playing in the lowest Verilog level (gate level).
I found this post:
https://electronics.stackexchange.com/questions/390661/is-it-possible-to-create-a-working-jk-flip-flop-using-gate-level-description-in
in that I could understand that shoud…
Carlos J.
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-2
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1 answer
Verilog If statement -Appears to be triggering before Condition
Why does r_D <= 8'h40 execute before w_Rx_DV == 1'b1 according to below code and waveform? R_D should not be assigned any value until w_Rx_DV goes high.
Thank you for any comments
Joe
module main(
input i_Clock,
input …
Joe Bingham
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