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I have an example project in Verilog originally was for ICE40 FPGA, I want to import it to Xilinx FPGA for resource reason. There is this SB_IO primitive in ICE40 that defines input/output ports. I don't quite understand it and wondering if there is similar or equivalent primitive in Xilinx FPGA? Or how to translate it into Xilinx FPGA domain?

The example code is as follows:

SB_IO #(
    .PIN_TYPE(6'b010100),
    .PULLUP(1'b0),
    .NEG_TRIGGER(1'b0),
    .IO_STANDARD("SB_LVCMOS")
) iob_data_I[SDW-1:0] (
    .PACKAGE_PIN(disp_data),
    .CLOCK_ENABLE(1'b1),
    .OUTPUT_CLK(clk),
    .D_OUT_0(phy_data)
);

Please help, thanks!

BZKN
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TerryL
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1 Answers1

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This looks like the SB_IO is being used as an output register. So the Xilinx equivalent would be FDRE or another DFF primitive with the (*IOB="TRUE"*) attribute set on it to encourage it to be packed into the IO register block.

gatecat
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