Icarus Verilog is an implementation of the Verilog HDL or hardware description language.
Icarus Verilog is the same as iverilog
Questions tagged [icarus]
70 questions
0
votes
1 answer
$dumpfile and $dumpvars not working in vscode error in terminal says requires system verilog
Elaboration task '$dumpvars' requires SystemVerilog
is the error that is showing in the terminal when I execute
iverilog -o test_tb.vvp test_tb.v
similar for $dumpvars
the codes are
//design
module test (a,b);
input a;
output b;
…
Chomusuke
- 3
- 1
0
votes
1 answer
Ring oscillator in Verilog/SystemVerilog - supressing undefined states
It is quite straightforward to write ring oscillator in Verilog.
It is also known that in reality regardless of initial state it will work reliably in real hardware, both in FPGA and ASIC form (if it's not optimized away).
But Verilog model without…
BarsMonster
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0
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1 answer
Why isn't ModelSIM displaying timing waveforms, whereas GTKWave does?
I am kinda new to verilog and struggling with all the basic concepts.
I am trying to display the timing waveform in ModelSim, where is simply throws "# (vish-4014) No objects found matching '/tb/*'. "(in my case).
Whereas when I simulate the…
afaq
- 111
- 2
0
votes
1 answer
How to test if a 3-bit bus has the first bit set on 1 - verilog
I'm trying to find out how could I check if a 3-bit bus has the msb set on 1, i.e. 1xx.
When I check bus==3'b1xx nothing seems to happen.
pauk
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0
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0 answers
I cannot see the contents of a memory
I have a problem when I try to simulate a circuit which is supposed to process data taken from an SRAM memory. Firstly, an SRAM memory is filled with data, this could be seen if one has a look over the last testbench, than, the stored data will be…
pauk
- 350
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- 15
0
votes
1 answer
why are icarus verilog specify times not respected?
My understanding of "specify" is that it controls the propagation delay from input to output.
So ..
I expect the code below to show 'o' changing at 118 - ie 10 time units after 108 when 'b' changed
but instead the 'b' change is incorporated at 115…
johnlon
- 167
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0
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1 answer
How to add all, except one file in iverilog command line instruction from a folder?
I understand that if I want to include all the Verilog files I can do so by adding files like this:
iverilog /Users/kp/Desktop/all_new2/*.v -s testbench.v
which takes all files in all_new2 folder and sets testbench.v as the top module. However, I…
Kiran
- 43
- 8
0
votes
1 answer
Passing a single row of a 2d array as an input to a module in verilog
I was wondering if there is any way to pass a single row of a 2d array of values as the input to a module in Verilog.
Say my array is defined like this:
reg[15:0] arr[0:9][0:63];
...
...
mod1 m(..., arr[5], ....);
mod1 has the…
Akilesh Kannan
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3 answers
verilog ; can't use "string" type in $display
I'm using a recent master branch build of icarus verilog.
Should I expect the following to run?
module string_display ();
//reg [10:0][7:0] x = "initial";
string x = "initial";
always @* begin
$display ("x = %s",x);
end
initial begin
//…
John Lonergan
- 305
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0
votes
1 answer
multi dimensional array ports support in icarus verilog
I am trying to use multi dimensional arrays as ports in my systemverilog code. the top module is a 3-dimensional array whereas the submodule is a 2-dimensional one. A simplified test bench and design is as follows:
module TB();
wire …
M.X
- 195
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0
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1 answer
icarus verilog specify delays not respected if there are conditionals
Trying to model a 74245 with delays representative of the HCT device.
I am finding that the timings I'm providing in a specify block are not respected.
I have added an extra route A->C (not part of my orig design) to illustrate that the delays can…
John Lonergan
- 305
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- 6
0
votes
1 answer
Verilog Full Adder Unexpected Behavior
I am trying to do a very basic hardware module/test bench to get the hang of Verilog. I have tried to implement a full adder.
If I am not mistaken, you have three input, immediate addends a and b and a carry in from the 2^n-1 place.
The outputs are…
Jack Frye
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0
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3 answers
iverilog recursive function causes segmentation fault
Here's the problematic code:
function automatic [31:0] W;
input [6:0] param;
W = (param<16) ? 32'b0 : W(param-7);
endfunction
Basically, iverilog (Icarus Verilog) just gives me a Segmentation fault: 11 vvp svsim error.
I tried a bit of…
unixb0y
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0
votes
1 answer
Reading file in Icarus Verilog
I have a file data.txt that has 1200 lines, each representing a 16 bit binary string such as the following.
"0001111111000000"
I'm trying to write a testbench using Icarus Verilog that reads in each line of the file and sends each line to a .v…
Ian
- 11
0
votes
1 answer
Unexpected high impedance state
I've encountered a problem of unexpected high impedance state on output ports of my modules. Code of the module that instantiates other modules is following:
`timescale 1ns/1ps
module column(
input wire clk,
input wire reset,
input wire…
Sergey Lapin
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