Highest Voted 'icarus' Questions

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Error opening .vcd file. No such file or directory

My Verilog code is stored in C:\FA. There are three files: FA.v, fa.vvp, TM_FA.v I followed my book steps. iverilog -o fa.vvp vvp fa.vvp finish getwave fa.vcd & When I use getwave fa.vcd & to simulate it, and then it shows: Error opening .vcd…

verilog icarus gtkwave

asked May 04 '21 at 14:12

Kias

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Behavioral Modeling is not a valid l-value in testbench.test

I am trying to use two binary inputs A and B to get the binary output which is the F just like the truth table below, but it keeps saying: main.v:36: error: F3 is not a valid l-value in testbench.test main.v:27: : F3 is declared here as…

verilog hdl icarus

asked Apr 09 '21 at 13:07

Connor Mcgee

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Why the memory content is not read? - verilog digital system design

I created a microsystem which is composed of two clocked SRAMs, one designed for storing instruction-codes, and another to store some output values. The instruction SRAM has an interface module, named "user" which provides a mechanism to ease the…

memory verilog system digital icarus

asked Jan 04 '21 at 14:43

pauk

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I see undefined output sequences reading a memory in simulation

I have a question related to the implementation of a clocked SRAM memory which is is supposed to store data written by user and then display the memory content. In addition, I created a module named display which eases the reading process so that…

memory verilog simulate test-bench icarus

asked Jan 03 '21 at 10:05

pauk

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Can't see anything when accessing RAM contents in simulation

I encountered an issue trying to design a SRAM memory. To be more specific, the memory is clocked, has a write enable - when high, one could write data and when low, one could read data - , an address input, which specifies the memory address…

memory verilog simulation hdl icarus

asked Jan 02 '21 at 13:58

pauk

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Cannot load/store data from/in SRAM: read data is unknown

I have a question related to a Verilog implementation of an SRAM memory. Module sram_1port is supposed to be a clocked address addressable SRAM memory which has a read enable signal and a write enable signal. Module control_sram is supposed to…

memory verilog icarus

asked Dec 01 '20 at 11:12

pauk

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Can't create a 'real' type array in Verilog

I've tried creating a 'real' type value array in the following way in Icarus Verilog: parameter width = 10; shortreal b [width-1:0] = {0.0181,0.0487,0.1227,0.1967,0.2273,0.1967,0.1227,0.0487,0.0181}; Gives the following error: error: Cannot assign…

arrays parameters verilog icarus

asked Oct 28 '20 at 07:26

Ginjas

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RisingEdge example doesn't work for module input signal in Chisel3

In Chisel documentation we have an example of rising edge detection method defined as following : def risingedge(x: Bool) = x && !RegNext(x) All example code is available on my github project blp. If I use it on an Input signal declared as…

hdl chisel icarus cocotb

asked Sep 10 '19 at 07:41

FabienM

3,421
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Incomprehensible For Loop Icarus Verilog

I am trying to follow the basic example provided here. https://www.youtube.com/watch?v=13CzlujAayc&list=PLUtfVcb-iqn8ff92DJ0SZqwsX4W1s_oab&index=17 Here is my exact code maj3.v module maj3(Out, A, B, C); input A, B, C; output Out; wire…

verilog test-bench icarus

asked Mar 23 '18 at 18:16

Jack Frye

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iverilog testbench error: input is declared as wire, but it isn't

I am very new to iverilog and am creating a counter to reduce a 100Mhz clock frequency to something easier to work with, as part of a larger project. I found some code that does that and so I tried to write a testbench for it. Here is the code I…

verilog test-bench iverilog icarus

asked Oct 31 '17 at 00:43

Ross Satchell

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Icarus Verilog crash while compiling dynamic memory module

This is my first post on StackOverflow. I'm a Verilog newbie, though I have significant experience with Python, C, and C++. I am using Icarus Verilog version 10.1.1 on Windows 10, and am trying to write a dynamic memory allocator. For some reason,…

crash verilog icarus

asked Oct 17 '16 at 21:15

Anonymous1847

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How to convert a VHDL code in Verilog using Icarus Verilog?

I can't find an example in doc to convert a VHDL code to Verilog with icarus. I found how to do verilog to VHDL here. I tried to modify the command to do VHDL convertion on this code : $ iverilog -tvlog95 -o button_deb.v button_deb.vhdl…

vhdl verilog icarus

asked Jan 06 '16 at 09:30

FabienM

3,421
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Verilog testbench code using gEDA and iVerilog

My assignment is to code a simple 2 to 4 decoder and then display the possible outcomes and waveform. I am using the gEDA suite along with Icarus Verilog (iVerilog) as a compiler and GTKWave for the waveform. This is my first time coding with…

verilog hdl icarus

asked Nov 25 '14 at 02:27

milleraj66

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Infinite loop when simulating a Program Counter design with Icarus Verilog

I am implementing a simple Program Counter adder with the following prototype: module program_counter(input enable_count, input enable_overwrite, input[31:0] overwrite_value, …

verilog infinite-loop program-counter icarus

asked Apr 06 '14 at 22:10

Patrick Samy

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how can I convince iverilog that the vpi is a system function and not a task

I am trying to use a vpi function in iverilog that will return a value to the verilog test bench after it is called. It compiles ok but returns the following when I run Error: $flash_dat() is a system task, it cannot be called as a function. I have…

verilog icarus

asked Dec 12 '12 at 06:12

vinay samuel

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Questions tagged [icarus]