Icarus Verilog is an implementation of the Verilog HDL or hardware description language.
Icarus Verilog is the same as iverilog
Questions tagged [icarus]
70 questions
0
votes
2 answers
viewing waveform using scansion
NOTE: if there is a better place for me to ask this, please let me know! I've googled extensively and cannot find an answer
I'm trying to view the output of a simple counter/sin LUT using the waveform viewer scansion. I am using icarus verilog to…
qasddd
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0
votes
1 answer
Extension to icarus
Is it possible to make an extension to icarus that listens to the events from the test run and handles the result on to ie. growl.
I have been searching the internets and could not find a way to do this.
THX
khebbie
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0
votes
1 answer
Could not attach debugger to host using Gallio Icarus 3.2 Build 517 and VS 2010
I installed the Gallio bundle Version 3.2 Build 517 in order to use MBUnit. My tests are running fine when I try run them through the Icarus test runner, but when I hit the debug button on the test runner, it tells me it could not attach to the…
Xaisoft
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0
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2 answers
Verilog 4x16 Decoder outputs wrong data
I have implemented a 4x16 Decoder using Verilog along with it's test. For each case the decoder should output a 16-bit digit with only one of the bits high. I can't manage to get all the desired outputs when I run the program. Here is the code for…
Lewis Rodriguez
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0
votes
1 answer
Verilog Build System for Sublime Text 3
I am trying to implement a simple build system for Verilog in Sublime Text, but I am getting the following error when I build:
[Errno 2] No such file or directory: 'iverilog'
[cmd: ['iverilog', '-o', 'iverilog/compiled',…
rp.beltran
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0
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1 answer
syntax error file of icarus verilos compiler
Does anyone know which file is the one which has the grammar in icarus verilog compiler? and also which one has the syntax error handing and printing?
thank you all in advance
0
votes
2 answers
Verilog 4-bit up-down counter designed using negative edge triggered T flip flops
I'm very new to Verilog HDL and I have to code this 4bit up down counter. With the help of some reading on up-down counters and t flipflops, I already made the following code:
module up_down_4bitcounter (
out,
up_down,
clk,
data,
reset
);
//Output…
Freeda Suing
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0
votes
1 answer
$rtoi() is not a constant system function
I want to set size of a constant for a counter:
localparam MAX_COUNT = ((debounce_per_ms * clk_freq)) + 1;
parameter MAX_COUNT_UPPER = $rtoi($floor($log10(MAX_COUNT)/$log10(2)));
That work well with XST (ise) and with verilator but in Icarus I've…
FabienM
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0
votes
1 answer
Tests run in Gallio / MbUnit fail; unable to load Castle DynamicProxy
I have a .NET 3.5 assembly covered by around 4000 MbUnit tests. I hve been running these using the mbunit.cons.exe program with no trouble.
Now I am trying to switch to Gallio (mbunit.cons.exe started blowing up with an 'out of memory' exception…
andypaxo
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0
votes
1 answer
Icarus Verilog: Multibit array parse error
What is the proper multibit array declaration in Icarus Verilog? I'm getting a parse error in this code
input [19:0] array [0:9]; but when I tried input [20*10-1] array;, there's no parse error but there are errors in my input/output.
ellekaie
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0
votes
2 answers
Why am I getting parse error in reg declaration?
I'm getting a parse error from line 15 of this code:
12: module DoShellSort(
13: input [10*20-1:0] toSort,
14: output [10*20-1:0] sorted
15: reg arrBitSize
16: );
Here's the part of my testbench where I'm initializing the input and reg…
ellekaie
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0
votes
2 answers
Implementing PIPO in verilog
I am looking to implement a 32-bit Parallel in-Parallel out in verilog HDL. Here is the code I have written...
module pipo(input_seq, answer,reset, clock);
input [31:0] input_seq;
input reset,clock;
output [31:0] answer;
always @…
sudeepdino008
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0
votes
2 answers
Icarus Verilog simulation : Scope index expression is not constant: i
I am simulating a 16 bit MIPS netlist in Icarus Verilog.
This is the error i get in testbench
mips_16_core_top_tb_0.v:144: error: Scope index expression is not constant: i
mips_16_core_top_tb_0.v:144: error: Unable to bind wire/reg/memory…
user2548629
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0
votes
1 answer
Cannot compile unisim code in iverilog
I have been trying to compile ICAP_SPARTAN6.v from the unisim librabries provided by xilinx using icarus verilog.
I get the compile error below:
/opt/Xilinx/14.3/ISE_DS/ISE/verilog/src/unisims/ICAP_SPARTAN6.v:79: syntax…
vinay samuel
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-1
votes
1 answer
localparam / parameter with unpack array : icarus
I am trying to initilize unpack parameter.
module dut #(parameter int arr[3])
(
input logic clk
);
endmodule
module main;
int t[3];
initial begin
t[0] = 0;
t[1] = 1;
t[2] = 2;
end
localparam int arr1[3] = t; //'{1,2,3};
localparam int A0 =…
nir
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