Reading file in Icarus Verilog

Question

I have a file data.txt that has 1200 lines, each representing a 16 bit binary string such as the following.

"0001111111000000"

I'm trying to write a testbench using Icarus Verilog that reads in each line of the file and sends each line to a .v file that will run some simple if statements on each line of the file (a simple classification algorithm).

My code is below.

// Verilog test bench for generate.v
`timescale 1ns/100ps
`include "generate.v"

module generate_tb;

$display('running test bench')

   integer               data_file    ; // file handler
   integer               scan_file    ; // file handler
   logic   signed [21:0] captured_data;
   `define NULL 0    

   initial begin
      $dumpfile("generate.vcd");
      $dumpvars(0, generate_tb);

      data_file = $fopen("./data.txt", "r");
      if (data_file == `NULL) begin
         $display("data_file handle was NULL");
         $finish;
      end
   end

   always @(posedge clk) begin
      scan_file = $fscanf(data_file, "%b\n", captured_data); 
      if (!$feof(data_file)) begin
         generate the_circuit(output, captured_data); // HERE
      end
   end

   $finish;
   endmodule

and my generate.v file:

module generate(actual_class, data_row);

   output actual_class;
   input  data_row;

   wire stby_flag ;
   wire       [0:15] vect;

   reg [0:1] classe;

   assign vect = data_row;

   always  @(posedge clk) begin
        if (vect[3] == 0) begin
            classe = 2'b10;
        end

        if (vect[11] == 0) begin
            classe = 2'b01;
        end

        if (vect[8] == 1 &&  vect[4] + vect[5] + vect[6] + vect[7] >= 3) begin
            classe = 2'b00;
        end

        if (vect[0] + vect[1] + vect[2] + vect[3] + vect[4] + vect[5] + vect[6] + vect[7] + vect[8] + vect[9] + vect[10] + vect[11] + vect[12] + vect[13] + vect[14] + vect[15] <= 1) begin
        classe = 2'b11;
    end

end

assign actual_class = classe;

endmodule

I am stuck on this part of the code. I'm not sure how I can call the generate.v file for each line of the file.

if (!$feof(data_file)) begin
             generate the_circuit(output, captured_data); // HERE
end

A better way to do this would be to save my data into and use $readmemb but I'm hoping to do it this way.

Any advice is much appreciated.

do *not* use verilog keywords as module names, i.e. `generate`. — Serge, Jan 03 '18 at 19:05

score 0 · Answer 1 · answered Jan 02 '18 at 21:15

To start off: it is a very bad idea to name your module after a reserved word 'generate'.

I'm not sure how I can call the generate.v

It is a module, not a function. You can not 'call' a module.

You read each line from the file and assign it to a input variable of the module. Make sure you wait long enough before reading the next line for your module (and all subsequent triggered modules) to finish processing the input. You can wait a number of clock cycles or use a 'ready' signal.

A better way to do this would be..

Maybe. If your pattern gets very big you need a big memory.

Reading file in Icarus Verilog

1 Answers1