Here's the problematic code:
function automatic [31:0] W;
input [6:0] param;
W = (param<16) ? 32'b0 : W(param-7);
endfunction
Basically, iverilog (Icarus Verilog) just gives me a Segmentation fault: 11 vvp svsim
error.
I tried a bit of debugging and it seems not to like the recursion, even though I have a recursion anchor.
Calling the function from within itself isn't an issue though. Tested that, too.
Any help is appreciated!
EDIT:
Here I have the piece of code that calls this function unsuccessfully:
always @(negedge clk) begin
t1 <= W(j);
end