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I see the following FIRRTL code emitted by Chisel:

cmem mem : SInt<64>[8]

and

infer mport _T = mem[io.address], clock

NOTE: my memory object is named "mem".

However in the firrtl 1.5.2 specification the terms "cmem", "infer", and "mport" do not occur.

Someone please explain these terms. Better yet, is there some spec I do not know about that explains them?

Daniel
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1 Answers1

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These are features of "CHIRRTL" a slightly higher level IR than FIRRTL that helps bridge the gap between Chisel and FIRRTL. These aren't documented in the FIRRTL spec, but they should be.

There's three constructs:

  1. cmem which declares a combinational read memory. This will map to a FIRRTL memory with read latency 0 and write latency 1.
  2. smem which declares a sequential read memory. This will map to a FIRRTL memory with read latency 1 and write latency 1.
  3. write/read/infer mport which declares a memory port that is a read port, a write port, or will be inferred as read or write.

These closely map to Chiel's Mem (cmem) and SyncReadMem (smem) constructs.

One of the first things that a FIRRTL compiler does is it removes these constructs and converts them to FIRRTL memories by figuring out how many ports it has, what are the clocks/enables of each port, and whether or not a port is a read, write, or read/write port.

The best existing documentation about this is inside CIRCT's documentation: https://circt.llvm.org/docs/RationaleFIRRTL/#chirrtl-memories

seldridge
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