2

I have some FIRRTL and I want to get a critical path / bottleneck analysis of the code so as to maximize the clock rate by minimizing the critical path.

I can write a weighted topological sort myself, but I do not know the weights that I should use for various circuit components as well as for and fanout slowdown.

I have heard the RISC-V grad students speak of running a critical path analysis when optimizing their chips, so the Chisel / RISC-V infrastructure must provide one. I would expect this to be a flag on the firrtl tool, but I see no such flag.

Daniel
  • 1,861
  • 1
  • 16
  • 24

1 Answers1

0

This is normally done through a Synthesis/PnR tool such as Genus/Innovous. While you could look at the FIRRTL/RTL to get a generalization regarding your design, there would be many factors that ultimately effect the timing.

For example, all other things being equal, a 4 combo gate path would run faster than a 5 combo gate path. The issue being where gates are placed, their drive strength (and your power requirements), routing, etc. would likely contribute more towards timing than the gates themselves.

l Steveo l
  • 516
  • 3
  • 11