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Questions tagged [armv8]

This tag is for questions regarding specifically version 8 of the ARM architecture - 32-bit or 64-bit. Questions about the 64-bit ARM execution state or instruction set should be tagged with [arm64].

Version 8 of the ARM architecture introduced a new 64-bit execution state (AArch64) with a new 64-bit instruction set (A64) as well as retaining and extending the existing 32-bit execution state (AArch32) and its instruction sets A32 ("ARM") and T32 ("Thumb").

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Google Play 64-bit requirement issue even i have provided 64 bit apk

I have been researching for the past 3 days and nights on this issue but whenever I am uploading android app bundle on Google Play Store but getting 64-bit requirement error on review.My app bundle is completely Java/Kotlin based with native support…
Jafar
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Integrate ARMv8 Crypto accelerated SHA256 into existing C implementation function

I am trying to employ an ARMv8/Aarch64 assembly implementation using hardware accelerated SHA256 transform/"data block ordering" through CPU Crypto extensions. The problem is I do not understand the difference between the existing void…
Rauli Kumpulainen
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is there a compiler flag for opening/closing flush-to-zero mode in c++ armv8?

my compiler is clang, I don't know how to open flush-to-zero mode in armv8, could anyone tell me? I find some flag like this-fdenormal-fp-math=[values],but it doesn't work.
庄嘉琪
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Does Connext DDS Pro support Nvidia Jetson TX2?

I'm using Nvidia Jetson TX2 with Ubuntu 16.04 aarch64 in my project. I need to subscribe data from other system using Connext DDS Pro v5.2 running on Windows x86 or x64. But RTI Connext DDS Pro didn't supply official pre-built package for ubuntu…
user3871174
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How to build and use PJSIP for different architectures than armeabi?

I succesfully compiled PJSIP library for Android. Sample project works without any problems when I build for default architecture armeabi. Now I tried to compile library for arch such as armeabi-v7a and arm64-v8a. Unfortunately when I add libraries…
Zygi
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How can I build ARMv8 aarch32 binary?

I'm using Mediatek X20 dev board and gcc-linaro-6.3.1-2017.05 version for benchmark aarch64 vs aarch32. So I want to build binaries as 2 types of aarch32 abi : lp64, ilp32. From gcc manual, (@ [toolchain_path]/share/doc/gcc/AArch64-Options.html) It…
soongk
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How do I fix "Segmentation fault (core dumped)" in assembly?

I am using ARMv8 for my coding. I am almost done my code, except I have run into a problem. When I run the code, I get the "Segmentation fault (core dumped)" Error. The issue arises because when the line commented with //THIS ONE A executes, it…
Erick P
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ARM Assembly Arrays

I am trying to figure out how arrays work in ARM assembly, but I am just overwhelmed. I want to initialize an array of size 20 to 0, 1, 2 and so on. A[0] = 0 A[1] = 1 I can't even figure out how to print what I have to see if I did it correctly.…
Absiel
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Flush/Invalidate range by virtual address; ARMv8; Cache;

I'm implementing cache maintenance functions for ARMv8 (Cortex-A53) running in 32 bit mode. There is a problems when I try to flush memory region by using virtual addresses (VA). DCacheFlushByRange looks like this // some init. // kDCacheL1 = 0;…
user3124812
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Confusion regarding ARM architecture used in Raspberry_Pi 4 Model B

I have a Raspberry Pi 4 Model B Rev 1.1 board. When I gave the command cat /proc/cpuinfo, I got below logs. processor : 0 model name : ARMv7 Processor rev 3 (v7l) BogoMIPS : 270.00 Features : half thumb fastmult vfp edsp…
rohit
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AES encryption do not work on ARM processor

I have a device with armv8 64 architecture and I want to use its instructions for accelerating AES. I found this code in Github which implements AES encryption: https://github.com/noloader/AES-Intrinsics/blob/master/aes-arm.c However, it is missing…
Per Mertesacker
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What is SP0 and SPn in AArch64?

If the exception is being taken at the same Exception level, the stack pointer to be used (SP0 or SPn) In a document of AArch64 exception vector table, an entry is selected based off the factor above. I couldn't find any useful information…
zoey1771
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"Synchronous Abort" handler, esr 0x96000004

I am trying to boot an ELF file using u-boot on the orangepi-lite2 board, which is based on an allwinnertech-H6 (Cortex-A53 CPU). The execution of my program is triggering an exception: elr: 000000004a004d60 lr : 000000004a004dac (reloc) elr:…
Jane
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Understanding AArch64 Translation Tables

I'm doing a hobby OS project and I an trying to get Virtual Memory set up. I had another project in an x86 architecture working with Page Tables but I am now learning ArmV8 now. Now, I now that the maximum amount of bits used for addressing is…
Tristan Dubé
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Invalidate range by virtual address in dcache_inval_poc(start,end); ARMV8; Cache;

I'm confused by the implementation of the dcache_inval_poc (start, end) as follows: https://github.com/torvalds/linux/blob/v5.15/arch/arm64/mm/cache.S#L134. There is no sanity check for the "end" address, but what will happen if the range (start,…
windxlnx
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