VHDL : signal initialisation

Question

I'm a beginner at VHDL and I have problems when to decide whether I should initialize my signal or not...

Here's an exemple :

            entity tatoo is 
            port (
            clk, reset : in std_logic;  
            opcode : in std_logic_vector(2 downto 0); 
            A, B : in std_logic_vector(3 downto 0);
            F : out std_logic_vector(3 downto 0)
            ); 

            architecture toota of tatoo is 
            signal Q : std_logic_vector(3 downto 0);

            begin

            process (clk, reset) -- register for F
            begin
                if(reset = '1')
                    then F <= "0000";
                elsif(Clk'event and Clk = '1')
                    then F <= Q;
                end if;
            end process;

            process(opcode, A, B) -- ALU
            begin

Should I initialize Q here ? => Q <= "0000"; ?

                case opcode is 
                    when "00" =>
                        Q <= "0000";
                    when "01" =>
                        Q <= A-B;
                    when "10" => 
                        Q <= B-A;
                    when "11" =>
                        Q <= A xor B;
                end case;
            end process;

Thanks a lot,

score 2 · Accepted Answer · answered May 29 '13 at 13:14

2

You need to initialise it somewhere, or you'll get a latch. Your suggestion is fine (though Q <= (others => '0') is more future-proof), of you could have a default/others branch in the case statement, where you give Q a default value. Basically, when you have a combinatorial process like this one, make sure that anything your drive always has a defined value whatever the value of the inputs may be. If not, you're inferring memory of some sort.

answered May 29 '13 at 13:14

EML

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Thanks for you response! I would also like to know, if I had just an alu (my second process), with F instead of Q, should I initialize my output F (at the same place I precised)? If I understood well, i should to make sure that I don't generate useless latch.. Thanks a lot! – ZouZou May 29 '13 at 13:19
Yes. Remember: a process "runs" when anything in the sensitivity list changes. If the process is triggered, and the process executes, but it does *not* assign anything to a signal that you are driving (in other words, some execution branches change the signal, and some don't), then the process must build in memory to keep the state of that signal unaltered. In other words, a latch. Put in default assignments somewhere so that all execution paths assign to the signal. – EML May 29 '13 at 13:49

VHDL : signal initialisation

1 Answers1