Is my VHDL 1-bit Behavioral ALU complete?

Question

This is my first time writing VHDL code, and I'm wondering if this simple ALU VHDL code is complete. Everything I can find is for more complex ALUs, but I just need to write this simple one.

The problem is as follows:

Write a behavioral model that represents a simple ALU with integer inputs and output, and a function select input of type bit. If the function select is ‘0’, the ALU output should be the sum of the inputs; otherwise the output should be the difference of the inputs.

entity ALU is
    port(x, y, func: in bit; z: out bit;);
end entity ALU;

architecture behav of ALU is
begin
    alu: process is
    begin
        case func is
            when "0" =>
                z <= x + y;
                wait on x, y;
            when "1" =>
                z <= x - y;
                wait on x, y;
        end case;
    end process;
end behav;

I'm not asking for a complete solution, rather just to know whether my code is everything I will need for this simple problem.

Thanks!

score 2 · Accepted Answer · edited Jun 01 '14 at 04:08

2

Your code will fail if the inputs x and y do not change, but the operator func does.

That being said, in all of the VHDL code I've ever seen, you would just use a sensitivity list instead of the wait statements.

process(func, x, y)
begin
    case func is
        when "0" =>
            z <= x + y;
        when "1" =>
            z <= x - y;
    end case;
end process;

or, if you are using VHDL-2008:

process(all)
begin
    case func is
    ...

edited Jun 01 '14 at 04:08

Morten Zilmer

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answered May 31 '14 at 23:02

Bill Lynch

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Awesome, thanks. I see what you mean now that you mention sensitivity lists - that would be more practical than wait. I'll implement that instead. – Drac May 31 '14 at 23:29
@Drac: The difference in your and sharth's process is not just a matter of practicality, it also determines what can be synthesized into hardware or not. I don't think the process with the wait statements will synthesize into what you want, if it will even synthesize at all. The code in this answer is a very standard method of implying combinatorial logic, which in this case is a 2-input mux. – Ciano Jun 01 '14 at 14:34

Is my VHDL 1-bit Behavioral ALU complete?

1 Answers1