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Questions tagged [addressing-mode]

An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

From Wikipedia (Addressing mode):

Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand (or operands) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

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In 32 bits Mips architecture, why load word instruction need an immediate offset if the memory has only 32 bits long address?

I was reading about 32 bits Mips architecture. As far as I Know Mips memory is indexed using 32 bit locations and each location contain 32 bits value. In load word instruction its in the following format : lw $t, offset($s) which means -> $t =…
Mason
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GNU Assembly: Loading a list of values into a register

The following GNU Assembly example for x86 is taken from the book "Programming from the Ground Up": 1 #VARIABLES: The registers have the following uses: 2 # 3 # %edi - Holds the index of the data item being examined 4 # %ebx…
Traiano Welcome
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Assembly 32-bit addressing size instead of 64-bit in 64-bit Mode

i have a question about 32-bit addressing size instead of 64-bit addressing size in 64-bit Mode func: movzx eax, al ; instead of movzx rax, al mov eax, DWORD [4 * eax + .data] ; instead of mov rax, QWORD [8 * rax + .data] ret …
ELHASKSERVERS
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Address-size override prefix in 64-bit or using 64-bit registers

in Assembly Addressing (64-bit), which way is better? mov cl, BYTE [ebx + .DATA] or mov cl, BYTE [rbx + .DATA] ? the opcode for first way is : 67 8a 4b .. and the opcode for second way is : 8a 4b .. so if we use 32-bit register, we need to…
ELHASKSERVERS
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What are the differences among flat address space,linear addresses,base address,effective address calculations

What are the differences among all these things : flat addresses ,base address , linear addresses , effective addresses, physical address , effective address calculations ???
Thành Công
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find addreses referenced by ss:[esp+28]

I need to find an address in a game and am not sure how segement offsets are handled. in ollydbg it shows me a datastructure is at: ss:[esp+28] esp = 0019DF94 ss = 002B so what is the actual addres of the structure? is it ss+esp+28?
Luke
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How to compare a byte of a string in Assembly (GAS)

I coded a program in nasm assembly that swaps lowercase characters with uppercase characters and viceversa. I am trying now to program the same with gas assembly, but I am having trouble with the syntax for the comparisons of the bytes. So far the…
Programmer Failure
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What does "[V+ECX*2-2]" refer to in memory exactly?

So i have this exercise to solve: "Given a vector V of x 16 bit integers, check if the vector only contains even numbers. If it is the case, EAX will equal 1, otherwise 0. x is saved at the address n and has 16 bits. Here is the solution: …
Horace Horvath
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how to sum two matrices element by element?

I am new to assembly and I would be grateful if you would help me with a piece of code on how to add two matrices and move the result in another matrix, in assembly language x86-32bit. The matrices are declared as 1d arrays. n dd 9 A dd…
pau37
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In 64-bit mode, does the ModRM.r/m value of 100b necessarily require a SIB byte to follow after you have preceded the instruction with a REX of 41?

The AMD64 Architecture Manual Volume 3 talks about when the r/m field of the ModRM byte has a value of 100b, a SIB byte must follow. I understand that this is because you give up the ability to use the SP register (which is normally designated with…
Paul McKneely
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Difference betwen Base and Displacement

I have some issues understanding two instructions I encountered. The first one is as follow: imul eax,DWORD PTR [esi+ebx*4-0x4] Does this instruction means => Take the value at the address you calculate between brackets multiply it by eax and…
Future Gadget
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Simple ARM instruction LDR base register offset question

|-----------------------------|------------------|-----------------------| | Executable file header | Text Size | 300 hex | |-----------------------------|------------------|-----------------------| | …
crystalizeee
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RISC access address greater than largest integer register

Let's say you are running a 32-bit RISC system. What instructions would you use to access a 64-bit memory address? In a CISC instruction set, you can simply pass the extra word using a multiword instruction. For example: 1a) JMP 1b) loAddress 1c)…
Jet Blue
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Post-increment and Pre-decrement addressing modes on Intel 80386

I know how these modes work on other processors, what I don't understand is why doesn´t the 80386 need the post-increment and pre-decrement addressing modes? Also what´s the relation between these addressing modes and the push and pop instructions?
Paper Airplanes
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Assembly, x86: How to push a label to the stack?

given the data: .section data data_set: .long 2,5,33,54,2,76,4,37,43,223,98,70,255 how do I push the start address of the data (and not the value in that address) to the stack? I tried this: pushl data_set which eventually (after trying to access…
talz
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