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Questions tagged [addressing-mode]

An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

From Wikipedia (Addressing mode):

Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand (or operands) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere.

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what does "mov offset(%rip), %rax" do?

Does rax get offset plus the address of this instruction, or the next? From a microcode point of view it might be easier if the answer was the next instruction.
Bing Bang
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What is the meaning of x86 instruction "call dword ptr ds:[00923030h]"?

What does the following x86 assembler instruction do? call dword ptr ds:[00923030h] It's an indirect call I suspect, but exactly how does it compute the address to the call?
Marek
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What does the exclamation mark mean in the end of an A64 instruction?

The documentation for LDP and STP gives an example instruction with an exclamation mark in the end: LDP X8, X2, [X0, #0x10]! Also the documentation about porting A32 PUSH/POP instructions into A64 gives the following examples: PUSH {r0-r1} ---> STP…
Serge Rogatch
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Why does this MOVSS instruction use RIP-relative addressing?

I found the following assembly code in disassembler (floating point logic c++). 842: movss 0x21a(%rip),%xmm0 I understand that when process rip will allways be 842 and this 0x21a(%rip) will be const. It seems a little odd to use this…
Vladimir Yanakiev
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Error moving a constant byte value into %ebx

I'm working through Computer Systems, A Programmer's Perspective (3rd edition), and Practice Problem 3.3 contains the following line: movb $0xF, (%ebx) I'm supposed to find out what's wrong with this line of x86-64 assembly, and the answer key…
Peter Delevoryas
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I'm not exactly sure what this x86 Add instruction is doing

I'm not exactly sure what this add instruction is doing: add 0x0(%rbp,%rbx,4),%eax If it were: add %rbx,%eax I know it would add the contents of rbx and the contents in eax and store them back into eax. However, the 0x0(%rbp,%rbx,4) is throwing me…
DomX23
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What does a comma in a parenthesis mean in the AT&T syntax for x86 assembly?

What does (register1, register2, 4) mean in AT&T assembly? For example: cmp %eax, (%esi, %ebx, 4)
Secret
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mov %eax,(%esp)

What is the difference between the following statements? mov %eax,%esp mov %eax,(%esp) I'm working on diffusing a binary bomb and am having trouble with a few of the mov and leal commands early on in the assembly.
arc
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Why does the mov instruction have use ax instead of two segment registers directly?

I see code like: mov ax, cs mov ds, ax mov es, ax Why can't I just compress this to: mov ds, cs mov es, cs Is the first way faster since its using the accumulator register? But that wouldn't seem intuitive since cs and ds are segment registers. Or…
samoz
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Motorola 68000 assembler syntax for Program Counter Indirect with Index

I've been putting together my own disassembler for Sega Mega Drive ROMs, basing my initial work on the MOTOROLA M68000 FAMILY Programmer’s Reference Manual. Having disassembled a considerable chunk of the ROM, I've attempted to reassemble this…
msbit
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How is effective address calculated with fs and gs registers

In x86_64, fs and gs registers involve in a limited form of segmentation. Just taking, fs as an example, how does fs register, FSBase MSR work together to generate the effective address? What happens if I change fs base without changing fs? Or does…
PoorGuy998
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Subtracting registers with an LEA instruction?

Does the LEA instruction support negative displacement? mov rax, 1 lea rsi, [rsp - rax] When I use the above code in my asm file I got the error: $ nasm -f macho64 test.asm $ error: invalid effective address I Know that we can do pointer…
user62453
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Offset by value in a register in MIPS

I have a register($t2) that has a randomly generated number which I then multiply by 4. My question is, is it possible to use the value in $t2 as an offset when using the lw instruction?
user2103851
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ARM assembly: auto-increment register on store

Is it possible to auto-increment the base address of a register on a STR with a [Rn]!? I've peered through the documentation but haven't been able to find a definitive answer, mainly because the command syntax is presented for both LDR and STR - in…
John S
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Using 8-bit registers in x86-64 indexed addressing modes

Is it possible to use the 8-bit registers (al, ah, bl, bh, r8b) in indexed addressing modes in x86-64? For example: mov ecx, [rsi + bl] mov edx, [rdx + dh * 2] In particular, this would let you use the bottom 8-bits of a register as a 0-255 offset,…
BeeOnRope
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