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Questions tagged [zynq]

Zynq refers to the Zynq-7000 family of SoCs. A Zync device is a fully featured ARM processor-based system-on-chip.

Zynq refers to Zynq-7000 All Programmable SoCs which are based on the Xilinx All programmable SoC architecture. They enable extensive system level differentiation, integration, and flexibility through hardware, software, and I/O programmability.

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Need help mapping pre-reserved **cacheable** DMA buffer on Xilinx/ARM SoC (Zynq 7000)

I've got a Xilinx Zynq 7000-based board with a peripheral in the FPGA fabric that has DMA capability (on an AXI bus). We've developed a circuit and are running Linux on the ARM cores. We're having performance problems accessing a DMA buffer from…
Timothy Miller
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Adding applications petalinux

I have a microzed board based on the xilinx 7000 series with petalinux OS installed and configured on it. There are compilers and support for C/C++ applications. However, how do I add and get applications like PERL/python compilers and scripts…
bobbydf
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Write data to sdcard zedboard

I want to write data to zedboard's sdcard. I am able to write data to DRAM. Now I want to read DRAM's data and write it Sdcard. I have followed this (http://elm-chan.org/fsw/ff/00index_e.html) but it does not fulfill my requirement. I am not able to…
Hammad urRehman
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Use of Xil_Out32 in Xilinx SDK

In Vivado I succesfully made a simple blockdiagram to control the LEDs of my Zybo board. I can observe that the offset address for my LEDs is: 0x4120 0000 and the High Address is 0x4120 FFFF. Now when I go to the SDK: #include…
user3488736
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What is a good interface for a Linux device driver for a co-processing peripheral

I've written some Linux device drivers but I am still at the level of newbie hack. I can get them working but that's all I can claim. So far, I've been able to work them into a model of write data using write() and read data using read(). I…
user2142412
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u-Boot VxWorks TFTP boot failure: " ERROR: booting os 'Unknown OS' (14) is not supported"

I am trying to boot VxWOrks using tftp for zynq. I have set the enviroment varibles for ipaddr, serverip, netmask accordingly and files are loaded in RAM succesfully. however, i get the following error when trying to boot the vxWorks image. There is…
Aparajuli
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Can Zynq-7000 be singled steped

I want to use linux for the ARM core of Zynq-7000. But have a quesion on: Can I single step debug the kernel from the IDE instead of just printk? Does the hard ARM core allows single step into the kernel and expose all the registers, flags, pc?
Splash
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Is there a way to send data from the FPGA logic on a Zedboard to an external CPU without involvement of the ZYNQ PS?

I am a high school student, who is not very familiar with FPGAs and the Xilinx line. I am running a ring oscillator module on a Zybo Z7 board. I am also running a counter module, which I want to sample at a high rate. I am currently sending the data…
Rahul Jayachandran
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Problem in AXI GPIO interrupt handling in ZYNQ

I have a custom ZYNQ7000-based board. I want to insert an AXI GPIO that directly generate an interrupt. I want to handle the interrupt in a kernel module. All things sound to be correct but it does not work. My Toolset: Petalinux 2021.2 installed on…
user20007168
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Gcc Force global variable to a given address using linker only

I'm trying to force a global variable to a specific address without modifying the source code. I'm well aware of solution such as: // C source code MyStruct globalVariable __attribute__((section(".myLinkerSection"))); // Linker script . =…
Lucas
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How to access XDMA BAR0 in Petalinux?

I have a block design and hardware configuration with a Zynq processor running Petalinux. I furthermore have an XDMA IP configured as a memory-mapped endpoint. I have configured BAR0 and BAR2 in the PCI BARs tab. I am trying to write a simple…
Hedam
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How To Convert .bit file to .bin

I am following a tutorial on how to program the PL at run time for my ZedBoard. Tutorial Here. But I am stuck on the step where it says to Convert.bit into.bin. From my understanding the difference between the two file types is that a bitstream…
RMarms
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Using migen or chisel HDL languages on pynq FPGA boards

I am currently using the pynq-z2 FPGA eval board manufactured by TUL to design applications. It has a Processor+FPGA SoC Zynq7020 on it. The pynq python package allows us to interact with the PS and PL quite well via jupyter notebooks. I wanted to…
abunickabhi
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USB host not working in initramfs [Yocto]

I am writing to you to ask you about the following: I am working on a custom embedded Linux distro for a Zynq700 based board. One of the features to be added is support for USB in host mode, which I have achieved. This way, with rootfs I have a…
afinfante
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missing externel ports when trying to configure constraints in vivado 2018.3

i made this design in vivado 2018.3: the synthesis runs ok , but after that when i open the synthesised design to do the port mapping i cant find find all the ports some are missing , and only 8 ports exist :
mounsif gahit
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