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Questions tagged [zynq]

Zynq refers to the Zynq-7000 family of SoCs. A Zync device is a fully featured ARM processor-based system-on-chip.

Zynq refers to Zynq-7000 All Programmable SoCs which are based on the Xilinx All programmable SoC architecture. They enable extensive system level differentiation, integration, and flexibility through hardware, software, and I/O programmability.

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how to avoid caching when using mmap()

I'm writing a driver in petalinux for a device in my FPGA and I have implemented the mmap function in order to control the device in the user space. My problem is that, also if I'm using vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); in…
arandomuser
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Zynq 7000: Minimum asm code to init cpu1 from cpu0

I'm trying to figure out the minimum requirements to initialize cpu1 from cpu0 in an amp configuration on a zynq-7000. I have a given FSBL that hands over to u-boot with which I copy both programs (cpu0/1) from flash to different locations in ram…
robsn
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Xilinx, Zynq, AXI4 interconnect. What are the performance implications of configuring register slice and data fifo options?

Consider an AXI4 Interconnect on the PL (FPGA) side. When I double click to see the available options, there is a tab in Slave interfaces. Containing the following options. What is the purpose of enabling register slice? Does outer refer to the…
CJC
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change in endianness while ethernet transmission

I work with zedboard and vivado v2017.3. I am trying to send data stored in a register(slv_reg0 in PL section of Zynq) pointed by baseaddr_p in the following program. I use lwip echo server application to read this address and send it to the PC via…
upasana
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Add kernel configuration options using configuration fragments in custom YOCTO layer

I am currently trying to modify the kernel configuration (overwrite default xilinx-linux layer configs) by adding configuration fragments to my custom layer like this : .bbappend file: FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}" SRC_URI =+…
Logen Sand
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Running Ada on the Zynq using a Digilent Zybo development board

I've been successfully using Vivado and the SDK to develop VHDL and C for the Zynq XC7Z010 on a Digilent Zybo board. I've also been using the GNAT GPS IDE to learn Ada targeted to an STM32F4 processor (using one of the supported development…
Max van Daalen
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bare metal assembly program on Zynq without Vivado/SDK

I have a question for those familiar with the Xilinx Zynq and associated design tools.... Is it possible to compile and run C code for the Zynq 7010 (Zybo dev board), WITHOUT using the Xilinx toolchain (Vivado/SDK)? Is it possible to assemble and…
asmvolatile
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Unresolved symbols when linking libgio.so with libz.so (linux)

The Short Version Linking my executable against several libraries, including libgio-2.0.so.0.4800.1 (libgio-2.0.so) and libz.so.1.2.8 (libz.so), I get two unresolved symbols - deflateSetHeader@ZLIB_1.2.2 and inflateGetHeader@ZLIB_1.2.2. Neither…
binky
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Can only instantiate 1 generic-uio device

I'm trying to expose interrupts to userspace using the uio_pdrv_genirq driver. However I can only instantiate 1 device in the devicetree, all subsequent devices fail the probe. The system is a zynq-7000 and the kernel version is 3.9.0-xilinx. The…
lenguador
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where in the memory of PS block of Zynq the captured image data is stored of Zynq Processor ? So that I can take it to PL block using AXI interface

I have a GigE camera. I am using Zynq board. Now using linux programming I program the PS part of Zynq processor and capture the video and Now I have imagebuffer variable which has the captured Image data. I want to take the data from PS to PL part…
user3217310
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Disabled DCache will prevent atomic_flag from being set

We are using a zynq-7000 based CPU, so an cortex-a9 and we encountered the following issue while using atomic_flags which are inside an library we are using (open-amp). We are using the second CPU on the SoC to execute bare-metal code. When…
hellow
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Invalidating a specific area of data cache without flushing its content

I'm currently working on a project using the Zynq-7000 SoC. We have a custom DMA IP in PL to provide faster transactions between peripherals and main memory. The peripherals are generally serial devices such as UART. The data received by the serial…
Caglayan DOKME
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/dev/mem or user space burst transfer; how to get faster /dev/mem access

setup I have a bunch of RAM on the PL (programmable logic / FPGA) side of a zync-7000 chip. This memory can be accessed both via the PL and PS (processing system / CPU) side. The plan is for the CPU to load a large GiB buffer and hand it off to the…
philn
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Zynq, Yocto Linux and Custom FPGA IP Block Workflow

I'm new to the Zynq devices and also to linux and the Yocto project. I now have a project where I need to implement a custom FPGA IP block and use it from a yocto generated linux distribution. Obviously I will have to write the linux drivers for…
tm71
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Trustzone: CPU0 non-secure and CPU1 Secure in

I am using zynq-7000(zed board) with A9 processor (dual core). I am trying to work with the Trustzone. I want to configure cpu1 to be running only in the secure world and cpu0 to be running a normal world application (petalinux). I read ug1019 and…
Khurram
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